JPS61198711A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To automate a die sorting test or shorten a chip development process by previously forming pads for discriminating a plural kind of LSI patterns at the specific positions of the patterns when the patterns, in which the shapes of chips and the positions of bonding pads are made the same, are arranged onto one wafer. CONSTITUTION:LSIs, such as gate arrays GA1, GA2, GA3, GA4, etc., which have the same chip size and specifications thereof differ, are formed onto one wafer. Since these LSIs are all composed in the same manner, two code pads 21, 22 for discrimination for discriminating the GA1-GA4 and input/output pads 1 and the like are shaped to a gate GA1 as the LSI regarding the gate GA1, and the gate GA1 is connected to a power supply VCC and a grounding GND in the inside of the GA1. Accordingly, GA1='00', GA2='01', GA3='10', GA4='11', etc. are acquired as codes required. The pads 1, 21, 22, etc. are shaped previously at the same positions.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device having a mask structure in which a plurality of types of LSIt+tans are arranged on one wafer.

[Technical background of the invention and its problems]

Conventionally, when configuring a single system using system LSIs, a plurality of types of masks are required, each corresponding to a plurality of types of LSIs forming the constituent elements.

In this case, conventionally, since one type (single function) of chips is configured on one wafer, a plurality of types of wafers corresponding to each type are manufactured and a die sort test is performed on each type. For this reason, in the past, the amount of work in step 1 leading up to the die sort test increased in proportion to the type of mask.
This was considered a major problem in the 1Ls Ifi construction, which required early development.

In order to solve this problem, one idea is to configure multiple types of chips required for the system configuration on a single wafer (i.e., to fabricate a wafer by apparently creating one type of mask). It will be done. However, in this case, when testing each chip on the wafer, it is necessary to distinguish the type (logical function) of each chip, and this discrimination work is often difficult.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and in a semiconductor integrated circuit device having a mask structure in which a plurality of types of LSI patterns are arranged on one wafer, each of the LSI patterns can be easily identified. An object of the present invention is to provide a semiconductor integrated circuit device that can easily automate die sort testing and further shorten the chip development process.

[Summary of the invention]

The present invention provides multiple types of LSI/? In a semiconductor integrated circuit device with a mask structure arranged on a single methane wafer, %LSI/#tan (unique depending on the type of titanium) is placed at a preset specific position of the LSI/#methane. One or more 79-tan identification pads were set to the following signal state.
Even in a configuration in which multiple types of LSI chips are formed on a single wafer, automatic type recognition of each chip can be easily performed, which can automate the die sort test and further improve the associated chip development process. Shortening can be easily achieved.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.
The figure is a diagram showing a chip arrangement structure on a wafer in one embodiment of the present invention. Dirt array GAJ on this wafer
, GA2. GA3 and GA4 are LSIs having the same chip size but different specifications.

FIG. 2 is an enlarged view of each of the chips described above, and here GAJ is shown as an example. In the figure, 1.1. . . . are input/output pads similar to the existing configuration. 2. ．． 2
．． are the types of dirt arrays (GA7.GA,',
These are two identification code pads provided to identify GAJ and GA4). This identification code? pad 2
As shown in Figure 3, 1.2° is internally connected to the 'power supply (
vcc) and ground (GND), the required code (G17="00", GA"="0"
1”.

Gk3="10", GA4="11") are obtained. Table 1 shows the code correspondence at this time.

Table-1 In addition, each of the above pads 1, 1. ..., 28,2. The positions of the above dirt arrays GAI, GA2. GA3゜GA4
Place both in the same position.

Here, the test operation of the LSI chip according to the above embodiment will be explained.

(1) On one wafer, multiple types of LSI chips required for the system, that is, a 4m gate array G
kl, GA2. G.A.? , GA4, and each of Katsuko's e-doors L/IGAI, GA2. GA3゜3rd to GA4
A unique identification code is set for each chip as shown in Table 1 by the means shown in the figure, and the code is output from the identification code pads 21 and 22 at a predetermined specific pad position. do.

(2) Input test programs and identification codes for various chips into the tester, and perform tests corresponding to the identification codes input to the fixed card (a card with pins that connect the input/output pads of the tester and the chip under test). Computer processing is performed to select a program.

(3) Each gate array GAI, GA2 . on the one wafer to be tested. G.A.? , GA4, even if the specifications are different, the chip size and the position of each pad are the same, so the fixed card movement distance is determined accordingly. Then, by aligning the fixed card with the starting point chip, the identification code band 2
Also, the identification code entered via □ and 2□ is
A test program corresponding to that chip is executed, and after the test program is finished, computer processing is performed so that the fixed card is automatically moved to the next chip.

(4) After completing the processes in (t) to (3), start the program by aligning the fixed card with the chip that is the starting point.

By performing a die sort test on a composite mask using the method described above, the repetition of steps in a conventional die sort test on a single mask wafer is eliminated. In other words, this means that multiple types of TSI are required to configure one system.
This means that a die sort test for chipping can be performed in a process similar to that for a single LSI. Therefore, effects such as labor saving during evaluation and early development by eliminating time loss can be obtained.

The above explanation is based on an example in which multiple types of LSI chips constituting one system are formed on one wafer.
The present invention is not limited to this, and can also be applied to a method in which multiple types of masks each having a /4' cross section of the same size are formed on one wafer.

〔Effect of the invention〕

As described in detail above, according to the present invention, in a semiconductor integrated circuit device using a mask in which a plurality of types of LSI patterns are arranged on one wafer, preset specific At the position, LSI/f button (chip)
1 or 1 set to a unique signal state depending on the type of
- By having a configuration in which multiple patterns are identified, it is easy to recognize the type of each wafer even when multiple types of LSI chips are formed on a single wafer. This allows automation of die sort testing,
Furthermore, the chip development process can be easily shortened accordingly.

[Brief explanation of drawings]

g4 is a diagram showing the chip arrangement structure on a wafer in one embodiment of the present invention, FIG. Identification code
- It is a diagram showing an example of the role status of Grado. GAZ, GA2, GA3, GA(-1"-
47 rays (LSI chip), 1, 1...input/output pad, 2□, 2□...m code pz4. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 vg1 Figure 3

Claims (1)

[Claims] In a semiconductor integrated circuit device having a mask structure in which multiple types of LSI patterns having the same chip shape and bonding pad positions are arranged on a single wafer, the above LS
A semiconductor integrated circuit characterized in that one or more pattern identification pads are provided at a preset specific position of each I pattern, each having one or more pattern identification pads set to a unique signal state depending on the type of the pattern. Device.