JPS61198765A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to miniaturization of the chip size of a semiconductor device.

The semiconductor device of the present invention achieves the above-mentioned miniaturization by using the surface of the semiconductor substrate directly under the external lead-out electrode section, which has not been used conventionally, as part of the input protection circuit or part of the element section. be.

[Prior Art] FIGS. 4 and 5 are diagrams showing a conventional semiconductor device.

The semiconductor device has a flip chip bump electrode (Fig. 4;
20) or a pounding pad (Fig. 5: 21)
), and these external lead-out electrode parts and an element part such as an integrated circuit are electrically connected by a wiring part 4.8. Note that the necessary locations are insulated by an insulator 1131.32 formed at a predetermined location on the surface of the substrate 1. Note that the wiring portion is formed of a wiring pattern 4.8 made of aluminum or the like.

However, in the conventional semiconductor device described above, no element part is formed on the semiconductor substrate directly under the external lead-out electrode part, and therefore, this part (range A in FIG. 4, range B in FIG. 5) is wasted. This results in an increase in chip size.

[Problems to be Solved by the Invention] The present invention has been devised in view of the above-mentioned circumstances, and it is possible to reduce the chip size by using the part directly under the external lead-out electrode part as a part of the element part. The goal is to achieve the following.

Means and operation for solving the problem [c] The present invention achieves miniaturization of a semiconductor chip by forming an impurity diffusion layer directly under the external lead-out electrode section and using this as a part of the element section. It is.

FIG. 1 is a schematic cross-sectional view of a semiconductor device as an example of the present invention. and a wiring section 4.8 connecting these, characterized in that a part of the element section is formed by an impurity diffusion layer 5 on the surface of the semiconductor substrate 1 directly under the external lead-out electrode section 2. This is a semiconductor device.

The element portion 5.6.7 (the integrated circuit portion continues to the right of the wiring pattern 8 in the figure) is a portion where various elements such as transistors, diodes, and resistors are formed, and is a well-known portion on the surface of the semiconductor substrate 1. Formed by a method (planar method, etc.).

The external lead-out electrode section 2 is an input/output terminal to the element section, and in the present invention, the flip chip bump li[ff1 (first
Figure; 2. 4; see 20) or a bonding pad for wire bonding (see FIG. 5: 21). In the case of a flip-chip bump electrode, the intermediate metal layer 24 and the aluminum wiring pattern 4 under the electrode are used to diffuse impurities directly under the electrode. It has a buffering effect against 5.

In the case of a bonding pad, it is preferable to configure the bonding pad into two layers in order to absorb shock during wire bonding. These external lead-out electrode portions 2 can be formed by a known method.

The wiring portion connects the element portion and the external lead-out electrode portion 2 and the element portions, and in the case of FIG. 1, is constituted by an aluminum wiring pattern 4.8. In addition, when the external lead-out electrode part 2 is an input terminal, the wiring part connected to it has a function as part of an input protection circuit. For example, the aluminum wiring pattern 4 functions as an input protection resistor.

The aluminum wiring pattern 4.8 can be formed by a known method such as vapor deposition.

The impurity diffusion layer 5 directly under the external lead-out electrode section 2, which is a feature of the present invention, can be formed by a known method such as a planar method when forming the element section.

In the case of FIG. 1, the impurity diffusion layer 5 and the external lead-out electrode section 2 are electrically connected at two locations (41, 42).

However, the present invention is not limited thereto, and the impurity diffusion layer 5 and the external lead-out electrode section 2 directly above the impurity diffusion layer 5 may not be electrically connected, and the impurity diffusion layer 115 may be connected to another external lead-out electrode section.

In the semiconductor device having the above configuration, an impurity diffusion layer 5 is formed directly under the external lead-out electrode section 2, and this is used as a part of the element section. Therefore, the utilization rate of the semiconductor substrate surface is improved,
This is useful for downsizing the device.

[Example] The present invention will be described below based on specific examples.

1 and 2 are schematic cross-sectional views of a semiconductor device according to an embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram of the device shown in FIGS. 1 and 2. In FIG. 1, the potential of the N'''' type semiconductor substrate 1 is maintained at Vcc, and in FIG. 2, the flip chip bump electrode 2' is grounded. Further, the aluminum wiring 8' in FIG. 2 is connected to the aluminum wiring 4 in FIG. 1. Note that each number shown in FIG. 3 corresponds to the number in FIG. 1, respectively. Furthermore, the resistor R6 is connected to the diffusion layer resistor 6 in FIG. 1, and the diodes D5 and D7.
correspond to a diode formed of the diffusion layer 5 and the N-type semiconductor substrate 1 (Vcc), and the diffusion layer 7 and the N'''' type semiconductor substrate 1 (Vcc), respectively.

In addition, the diode D5- is connected to the diffusion layer P- (P
+) type layer 1-(5-17"). (5- and 7' are in a conductive state (same potential). 1' is 9 and N"" substrate 1 In this embodiment, the flip-chip bump electrode 2, which is an external lead-out electrode part, is connected to the impurity diffusion layer 115 formed directly below it, and the impurity diffusion layer 5 This is a case where the input protection circuit is used as part of an input protection circuit. Also, an N'''' type substrate is used as the semiconductor substrate.

(Manufacture of Semiconductor Device) First, a part of an element part and a wiring part are formed on the surface of an N-type semiconductor substrate 1 by a planar method. Here, P-type impurity diffusion layers 5.7.5', 7' and P-type diffusion layer resistance 6.6
', and N-type diffusion Fr19 are MOS formed in the element part.
It can be formed simultaneously with the l-transistor (not shown).

Next, after oxidizing the surface of the semiconductor substrate to form an oxide film 31, windows are opened in the oxidized film 31 at predetermined locations 41, 42, 81, 41-181', and then aluminum is deposited on the entire surface. After that, unnecessary aluminum was removed by etching at the specified locations 41, 42, 8.
1. Wiring patterns 4.8.4', 8- connected to the diffusion layers 5.7.5', 9 are obtained at 1.41-181-.

After forming the above wiring pattern, an insulating film of silicon nitride (3i3Nn>) or an SiO2 film by sputtering is formed on the entire surface using a plasma CVD method, and a window is opened in the part of the insulating film 32 where the flip-chip bump electrode is to be formed. Thereafter, an intermediate metal film 24, 24' is deposited on the window opening, and an electrode base 23' is formed on the intermediate metal 124, 24'.
．． 23' and solder bumps 22 and 22', respectively.

(Evaluation) The semiconductor device formed as described above has a P-type impurity diffusion layer 5.5-1 immediately below the flip chip bump electrode 2.2'.
1' and an N-type impurity diffusion layer 9 are formed, which are used as part of the input protection circuit of the wiring section. That is, the diode 05.07 functions as a protection diode against excessive positive input, and the diode D5- functions as a protective diode against excessive negative input. Therefore, unlike the conventional method, this portion of the substrate surface is not wasted, and the chip size can be reduced.

Further, the impurity diffusion layers 5.5' and 1-19 are connected to bump electrodes 2.5' and 1-19.
2-, the impurity diffusion 115.5
-11', protection diodes Ds, D formed by 9
It was possible to make s- larger in area than before, and it was possible to provide a protection diode with desired performance. Note that in this application, it is also possible to increase the area of the diode with respect to the substrate of the output transistor.

Furthermore, since the protection diode is configured directly under the flip-chip bump electrode, the protection resistor can be formed in the area where the protection diode was conventionally formed, and therefore the length of the protection resistor can be made longer than in the past. A protective resistor with a desired resistance value could be obtained.

[Effects] In short, the present invention forms an impurity diffusion layer directly under the external lead-out electrode section and utilizes this as a part of the element section.

As is clear from the description of the embodiments, in the device of the present invention, the area directly below the external lead-out electrode portion is used as a part of the element portion, and unlike the prior art, it is not wasted. Therefore, the chip size can be reduced.

In addition, when an impurity diffusion layer formed directly under the external lead-out electrode part is connected to the external lead-out electrode part, the area of the protection diode formed by the diffusion layer can be made larger than before, and the desired performance can be protected. You can get a diode.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view of another flip-chip bump electrode portion of the semiconductor device. Moreover, FIG. 3 is an equivalent circuit diagram of the apparatus shown in FIGS. 1 and 2. FIG. 4 is a schematic cross-sectional view of a semiconductor device having a conventional flip-chip bump electrode, and FIG. 5 is a plan view of a semiconductor device for wire bonding. 1... N-type semiconductor substrate 2... External lead-out electrode section 4... Wiring pattern 5.9... Impurity diffusion layer 6... Diffused layer resistance Patent applicant Nippondenso Co., Ltd. Agent Patent attorney Hirodo Okawa, Patent Attorney Shudo Fujitani, Patent Attorney Akio Maruyama (+J. m' Figure 3, Figure 4, Figure 5)

Claims (3)

[Claims] (1) In a semiconductor device having an element part formed on a semiconductor substrate, an external lead-out electrode part, and a wiring part connecting these, the element part is formed by an impurity diffusion layer on the surface of the semiconductor substrate directly under the external lead-out electrode part. A semiconductor device characterized in that a part of is formed. (2) The semiconductor device according to claim 1, wherein the impurity diffusion layer is connected to the external lead-out electrode section located directly above the impurity diffusion layer. (3) The semiconductor device according to claim 1, wherein the element section includes a MOS transistor, and the impurity diffusion layer is connected to the gate electrode of the MOS transistor as part of an input protection circuit.