JPS61198769A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS61198769A
JPS61198769A JP60039141A JP3914185A JPS61198769A JP S61198769 A JPS61198769 A JP S61198769A JP 60039141 A JP60039141 A JP 60039141A JP 3914185 A JP3914185 A JP 3914185A JP S61198769 A JPS61198769 A JP S61198769A
Authority
JP
Japan
Prior art keywords
rom
case
chip carrier
ceramic
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60039141A
Other languages
Japanese (ja)
Inventor
Masato Murata
村田 真人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60039141A priority Critical patent/JPS61198769A/en
Publication of JPS61198769A publication Critical patent/JPS61198769A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W78/00Detachable holders for supporting packaged chips in operation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/10159Memory
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/10515Stacked components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/1053Mounted components directly electrically connected to each other, i.e. not via the PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/301Assembling printed circuits with electric components, e.g. with resistors by means of a mounting structure
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/325Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by abutting or pinching; Mechanical auxiliary parts therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07541Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To reduce the size of the outer configuration, by arranging a chip carrier, on which a ROM is mounted, and conducting rubber in a recess in a ceramic case, fixing the chip carrier to the ceramic case itself, thereby omitting a fixed frame. CONSTITUTION:As an electronic circuit substrate for a hybrid integrated circuit, a ceramic case 1, in which a ROM mounting recess 5 is formed, is used. In said case 1, electronic circuits other than the ROM are incorporated. The recess 5 is a region, in which conducting rubber 6 and a chip carrier 7, on which the ROM is mounted, are placed. The conducting rubber 6 is put beneath the chip carrier 7. The ROM and the rubber are fixed to the case 1 by a cap 8 for compressing the ROM and the conducting rubber. Outer leads 2 are taking out of the case 1. A ceramic cap 3 is connected to the case 1 by solder 4. The chip carrier function is provided in the ceramic case itself. The hybrid integrated circuit is made compact, and its price is made low.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、再曹込み可能な読み出し専用メモリEPRO
M  またニ読み出し専用のメモIJPROM等のRO
Mを搭載する混成集積回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a refillable read-only memory EPRO.
M Also read-only memory IJPROM, etc. RO
The present invention relates to a hybrid integrated circuit equipped with M.

〔従来の技術〕[Conventional technology]

第31框従来列を示す分解斜視図、第4図は第3図の組
立状態を示すB−B線断面図である。
FIG. 4 is an exploded perspective view showing the 31st conventional stile row, and FIG. 4 is a sectional view taken along the line BB showing the assembled state of FIG. 3.

従来、EPROM FROMをチップキャリア7に搭載
し、これらの几(JM′t−、他の電子回路と電気的に
切!7離したり、接続したりする几めに、1’UMを固
定する固定枠11をセラミックケースIK:適当な接着
材12にエリ固定し、前記チップキャリア7お工び4を
性ゴム6tセラミックケース1に搭載する。この場合チ
ップキャリア7の下面に設けられた電極とセラミックケ
ース1の相対する面に配置し几電極との電気的接続を得
る几めに顧N固定用キャップ8により導電性ゴムを圧着
する。
Conventionally, the EPROM FROM was mounted on a chip carrier 7, and a fixing device was used to fix the 1'UM in a way to electrically disconnect from or connect to other electronic circuits. The frame 11 is fixed to the ceramic case IK with a suitable adhesive 12, and the chip carrier 7 is mounted on the rubber 6t ceramic case 1. In this case, the electrodes provided on the bottom surface of the chip carrier 7 and the ceramic A conductive rubber is placed on the opposing surface of the case 1 and crimped with a cap 8 for fixing the cap 8 in order to establish an electrical connection with the electrode.

ICチップ9t−Au−8iにLるハードマウント法又
は、Agペーストを用いたソフトマウント法にエリダイ
ボンディングし、Au線もしくはAu線等の配線用ワイ
ヤ10にエリワイヤーボンディングレ、ROM以外の電
子回路を構成する。ICチップ9の耐湿性の保護または
、前記配線ワイヤー10の保護は適当な外装比とえは、
シリコン系樹脂、エポキシ樹脂もしくは、セラミックキ
ャップを低融点ガラス等に10封止する。
Electronics other than ROM are bonded to the IC chip 9t-Au-8i by hard mounting method or soft mounting method using Ag paste. Configure the circuit. To protect the moisture resistance of the IC chip 9 or to protect the wiring wire 10, use an appropriate exterior ratio, for example,
A silicon resin, epoxy resin, or ceramic cap is sealed in low melting point glass or the like.

〔発明が解決しょうとする問題点〕[Problem that the invention seeks to solve]

従来に、固定枠11を特別に設ける必要がありコストが
高いという欠点があった。また、従来の回路は、その高
さが高く製品全体の外形サイズ2大きくしなければなら
ない。
Conventionally, there has been a drawback that it is necessary to specially provide the fixed frame 11 and the cost is high. Furthermore, the conventional circuit has a high height, and the overall external size of the product must be increased by 2.

本発明に、従来の固定枠11t−無くしコス)1−安く
することを目的とする。
An object of the present invention is to reduce the cost of eliminating the conventional fixed frame 11t.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の混成集積回路に、電子回路を内蔵しくぼみを有
する電子回路用基板と、導電性ゴムと、R(JM’i搭
載したチップキャリアと、前記チップキャリアを前記導
電性ゴムを介して前記くぼみ内に圧着して前記几UMを
前記電子回路に接続するキャップとを有することを特徴
とする。
The hybrid integrated circuit of the present invention includes an electronic circuit board having a built-in recess, a conductive rubber, a chip carrier mounted with R(JM'i), and and a cap that is crimped into the recess to connect the box UM to the electronic circuit.

〔実施例〕〔Example〕

第1図は本発明の一実施例を示す分解斜視図、第2図は
@1図の組立状態金示すA−A線断面図である。ROM
t−搭載したチップキャリア7及び導電性ゴム6′t−
搭載する領域全確保するくぼみ5をセラミックケース1
に設ける。セラミックケース1ににR(JM以外の電子
回路が組込まれる。電子回路に一例として積層セラミッ
ク多層基板技術を用いれば、容易に形成できる。またく
ぼみ5も積層セラミック基板1tたとえば金型にエリ打
抜く事にエリ容易[形成できる。さらに% ICチッグ
9t−Au−8i[よるハードマウント法又i、Agペ
ーストを用いたソフトマウント法にエフダイボンディン
グしs Au線もしくiAJ線等の配置用ワイヤlOに
ニジワイヤーボンディングし、別の電子回路を構成する
こともできる。ICチップ9の耐湿性の保護またに、前
記配線ワイヤー10の保護に適当な外装たとえば、シリ
コン系樹脂、エポキシ系樹脂もしく框、セラミックキャ
ップを低融点ガラス等にエフ封止する。
FIG. 1 is an exploded perspective view showing an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line A--A showing the assembled state shown in FIG. ROM
t-Mounted chip carrier 7 and conductive rubber 6't-
Ceramic case 1 has a recess 5 that secures the entire mounting area.
Provided for. An electronic circuit other than R (JM) is incorporated into the ceramic case 1.It can be easily formed by using a laminated ceramic multilayer substrate technology for the electronic circuit.The recess 5 can also be formed by punching an edge into the laminated ceramic substrate 1t, for example, in a mold. It is especially easy to form.Furthermore, it can be formed by hard mounting method using IC chip 9t-Au-8i, or by F-die bonding using soft mounting method using Ag paste. It is also possible to configure another electronic circuit by bonding the IC chip 9 with a rainbow wire.In order to protect the moisture resistance of the IC chip 9 and to protect the wiring wire 10, a suitable exterior material such as silicone resin, epoxy resin or the like can be used. Seal the frame and ceramic cap with low melting point glass, etc.

第2図にセラミックキャップ3全半出4により封止した
場合の一例?示す。R,(JMを搭載し几チップキャリ
ア7[4を性ゴム6を下に敷きROM固定用キャップ8
にエリ、セラミックケース1に固定される。この場合、
導電性ゴム6が圧着されチップキャリアの下面に設けら
れた電極とセラミックケースの相対する如く設けられた
電極とを電気的に接αし、所望の電子回路を構成する。
Fig. 2 shows an example of sealing with a ceramic cap 3 fully exposed 4? show. R, (with JM installed, place the chip carrier 7 [4] on the rubber band 6 and place the ROM fixing cap 8
Then, it is fixed to the ceramic case 1. in this case,
A conductive rubber 6 is crimped to electrically connect the electrode provided on the lower surface of the chip carrier and the opposing electrode provided on the ceramic case to form a desired electronic circuit.

〔発明の効果〕〔Effect of the invention〕

本発明に工れば、セラミックケース自体に、チップキャ
リア全固定する機能があるために、従来の固定枠を特別
に作製する必要が無く、従って従来の回路に比べて安価
にできる。tた、本発明に工れば、外形サイズを小さく
できる。
According to the present invention, since the ceramic case itself has the function of completely fixing the chip carrier, there is no need to specially manufacture a conventional fixing frame, and the cost can therefore be reduced compared to the conventional circuit. Furthermore, by incorporating the present invention, the external size can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

!!1図に本発明の一実施例を示す分解斜視図、第2図
にgi図の組立状態を示すA−A線断面図、i1!3図
は従来例を示す分解斜視図、第4図に第3図の組立状態
金示すB−B@1iiFr面図である。 1・・・・・・セラミックケース、2・・・・・・外部
リード端子、3・・・・・・セラミックキャップ、4・
・・・・・半田、5・・・・・・ROM搭載用くぼみ、
6・・・・・・導電性ゴム、7・・・・・・ROMTh
搭載したチップキャリア、8・・・・・・・・・ROM
及び導電性ゴム圧接用キャップ、9・・・・・・ICチ
ップ、10・・・・・・配線用ワイヤ、11・・・・・
・固定枠、12−・・・・・ROM固定固定用着接着用
接着A # l 図
! ! Figure 1 is an exploded perspective view showing one embodiment of the present invention, Figure 2 is a sectional view taken along line A-A showing the assembled state of Figure gi, Figures i1!3 are exploded perspective views showing the conventional example, and Figure 4 is FIG. 4 is a BB@1iiFr plane view showing the assembled state shown in FIG. 3; 1... Ceramic case, 2... External lead terminal, 3... Ceramic cap, 4...
...Solder, 5...Recess for mounting ROM,
6... Conductive rubber, 7... ROMTh
Equipped with chip carrier, 8...ROM
and conductive rubber pressure bonding cap, 9...IC chip, 10...wiring wire, 11...
・Fixing frame, 12-・・・Adhesive for fixing ROM A #l Figure

Claims (1)

【特許請求の範囲】[Claims]  電子回路を円蔵しくぼみを有する電子回路用基板と、
導電性ゴムと、ROMを搭載したチップキャリアと、前
記チップキャリアを前記導電性ゴムを介して前記くぼみ
内に圧着して前記ROMを前記電子回路に接続するキャ
ップとを有することを特徴とする混成集積回路。
An electronic circuit board having a recess for storing an electronic circuit;
A hybrid device comprising a conductive rubber, a chip carrier on which a ROM is mounted, and a cap that presses the chip carrier into the recess through the conductive rubber to connect the ROM to the electronic circuit. integrated circuit.
JP60039141A 1985-02-28 1985-02-28 Hybrid integrated circuit Pending JPS61198769A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60039141A JPS61198769A (en) 1985-02-28 1985-02-28 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60039141A JPS61198769A (en) 1985-02-28 1985-02-28 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS61198769A true JPS61198769A (en) 1986-09-03

Family

ID=12544827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60039141A Pending JPS61198769A (en) 1985-02-28 1985-02-28 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS61198769A (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02135768A (en) * 1988-11-16 1990-05-24 Sanyo Electric Co Ltd Hybrid integrated circuit
JPH02138768A (en) * 1988-11-18 1990-05-28 Sanyo Electric Co Ltd Hybrid integrated circuit device
EP0312802A3 (en) * 1987-09-24 1990-10-10 Elastomeric Technologies, Inc. Self-mounted chip carrier
JPH02125371U (en) * 1989-03-23 1990-10-16
JPH0371663A (en) * 1989-08-10 1991-03-27 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH0371662A (en) * 1989-08-10 1991-03-27 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH0371664A (en) * 1989-08-10 1991-03-27 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH0391951A (en) * 1989-09-04 1991-04-17 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH0391950A (en) * 1989-09-04 1991-04-17 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH0397255A (en) * 1989-09-11 1991-04-23 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH0397256A (en) * 1989-09-11 1991-04-23 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH03104152A (en) * 1989-09-18 1991-05-01 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH03104154A (en) * 1989-09-18 1991-05-01 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH03104153A (en) * 1989-09-18 1991-05-01 Sanyo Electric Co Ltd Hybrid integrated circuit device
FR2757682A1 (en) * 1996-12-20 1998-06-26 Thomson Tubes Electroniques METHOD AND DEVICE FOR CONNECTING A SEMICONDUCTOR COMPONENT TO A SUBSTRATE PROVIDED WITH CONDUCTORS

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0312802A3 (en) * 1987-09-24 1990-10-10 Elastomeric Technologies, Inc. Self-mounted chip carrier
JPH02135768A (en) * 1988-11-16 1990-05-24 Sanyo Electric Co Ltd Hybrid integrated circuit
JPH02138768A (en) * 1988-11-18 1990-05-28 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH02125371U (en) * 1989-03-23 1990-10-16
JPH0371663A (en) * 1989-08-10 1991-03-27 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH0371662A (en) * 1989-08-10 1991-03-27 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH0371664A (en) * 1989-08-10 1991-03-27 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH0391950A (en) * 1989-09-04 1991-04-17 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH0391951A (en) * 1989-09-04 1991-04-17 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH0397255A (en) * 1989-09-11 1991-04-23 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH0397256A (en) * 1989-09-11 1991-04-23 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH03104152A (en) * 1989-09-18 1991-05-01 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH03104154A (en) * 1989-09-18 1991-05-01 Sanyo Electric Co Ltd Hybrid integrated circuit device
JPH03104153A (en) * 1989-09-18 1991-05-01 Sanyo Electric Co Ltd Hybrid integrated circuit device
FR2757682A1 (en) * 1996-12-20 1998-06-26 Thomson Tubes Electroniques METHOD AND DEVICE FOR CONNECTING A SEMICONDUCTOR COMPONENT TO A SUBSTRATE PROVIDED WITH CONDUCTORS
WO1998028791A1 (en) * 1996-12-20 1998-07-02 Thomson Tubes Electroniques Method and device for connecting a semiconductor component on a substrate provided with conductors

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