JPS61199057U - - Google Patents

Info

Publication number
JPS61199057U
JPS61199057U JP8282185U JP8282185U JPS61199057U JP S61199057 U JPS61199057 U JP S61199057U JP 8282185 U JP8282185 U JP 8282185U JP 8282185 U JP8282185 U JP 8282185U JP S61199057 U JPS61199057 U JP S61199057U
Authority
JP
Japan
Prior art keywords
terminals
circuit
capacitor block
capacitor
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8282185U
Other languages
Japanese (ja)
Other versions
JPH0447967Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985082821U priority Critical patent/JPH0447967Y2/ja
Publication of JPS61199057U publication Critical patent/JPS61199057U/ja
Application granted granted Critical
Publication of JPH0447967Y2 publication Critical patent/JPH0447967Y2/ja
Expired legal-status Critical Current

Links

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の混成回路の実施例を示す斜視
図、第2図は第1図の長さ方向からの正面図、第
3図はコンデンサブロツクの拡大横断面図、第4
図は実施例における接続の説明図、第5図は実施
例の回路図である。 1:入力端子、2,3:出力端子、Vc:電源
端子、E:アース端子、10:コンデンサブロツ
ク、11:フラツトパツケージ、12A,12B
:電極、13A,13B,13C:溝、14A,
14B,14E:電極端子、15:端子、16:
主表面、17:導体パターン、18A,18B,
18C:端子、19D,19E,19G,19X
,19Y:外部端子、20:溝。
Fig. 1 is a perspective view showing an embodiment of the hybrid circuit of the present invention, Fig. 2 is a front view from the longitudinal direction of Fig. 1, Fig. 3 is an enlarged cross-sectional view of the capacitor block, and Fig. 4
The figure is an explanatory diagram of connections in the embodiment, and FIG. 5 is a circuit diagram of the embodiment. 1: Input terminal, 2, 3: Output terminal, Vc: Power supply terminal, E: Earth terminal, 10: Capacitor block, 11: Flat package, 12A, 12B
: Electrode, 13A, 13B, 13C: Groove, 14A,
14B, 14E: Electrode terminal, 15: Terminal, 16:
Main surface, 17: Conductor pattern, 18A, 18B,
18C: terminal, 19D, 19E, 19G, 19X
, 19Y: external terminal, 20: groove.

Claims (1)

【実用新案登録請求の範囲】 (1) 複数の独立したコンデンサが内部に形成し
てあり、夫々のコンデンサの電極の端を側辺に露
呈させてある板状のコンデンサブロツクと集積回
路のパツケージを重ね合せると共にコンデンサブ
ロツクの主表面に回路素子を固着してあり、該回
路素子、前記コンデンサ、集積回路を該集積回路
の端子を用いて相互に接続してなることを特徴と
する混成回路。 (2) コンデンサブロツク側に接続する集積回路
の端子は該コンデンサブロツクの側辺に固着して
いる実用新案登録請求の範囲第(1)項記載の混成
回路。 (3) コンデンサブロツク側に接続する集積回路
の端子は該コンデンサブロツクの側辺に固着する
と共に、少なくとも1つの該端子およびコンデン
サブロツク側に接続しない端子は外部端子に接続
され、外部端子が全体の樹脂封止された部分の外
側に露呈している実用新案登録請求の範囲第(1)
項記載の混成回路。
[Claims for Utility Model Registration] (1) A package consisting of a plate-shaped capacitor block and an integrated circuit in which a plurality of independent capacitors are formed inside and the ends of the electrodes of each capacitor are exposed on the sides. 1. A hybrid circuit characterized in that the circuit elements are superimposed on each other and a circuit element is fixed to the main surface of the capacitor block, and the circuit element, the capacitor, and the integrated circuit are interconnected using terminals of the integrated circuit. (2) The hybrid circuit according to claim 1, wherein the terminals of the integrated circuit connected to the capacitor block are fixed to the sides of the capacitor block. (3) The terminals of the integrated circuit connected to the capacitor block side are fixed to the sides of the capacitor block, and at least one of the terminals and the terminals not connected to the capacitor block side are connected to external terminals, and the external terminals are connected to the entire circuit. Utility model registration claim No. 1 that is exposed outside the resin-sealed part
Hybrid circuit as described in section.
JP1985082821U 1985-05-31 1985-05-31 Expired JPH0447967Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985082821U JPH0447967Y2 (en) 1985-05-31 1985-05-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985082821U JPH0447967Y2 (en) 1985-05-31 1985-05-31

Publications (2)

Publication Number Publication Date
JPS61199057U true JPS61199057U (en) 1986-12-12
JPH0447967Y2 JPH0447967Y2 (en) 1992-11-12

Family

ID=30630882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985082821U Expired JPH0447967Y2 (en) 1985-05-31 1985-05-31

Country Status (1)

Country Link
JP (1) JPH0447967Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052637U (en) * 1983-09-16 1985-04-13 日本特殊陶業株式会社 Ceramic package for semiconductor IC with capacitor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052637U (en) * 1983-09-16 1985-04-13 日本特殊陶業株式会社 Ceramic package for semiconductor IC with capacitor

Also Published As

Publication number Publication date
JPH0447967Y2 (en) 1992-11-12

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