JPS61199196U - - Google Patents
Info
- Publication number
- JPS61199196U JPS61199196U JP8168585U JP8168585U JPS61199196U JP S61199196 U JPS61199196 U JP S61199196U JP 8168585 U JP8168585 U JP 8168585U JP 8168585 U JP8168585 U JP 8168585U JP S61199196 U JPS61199196 U JP S61199196U
- Authority
- JP
- Japan
- Prior art keywords
- control circuit
- frequency control
- circuit
- frequency
- restored
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000452 restraining effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Landscapes
- Control Of Ac Motors In General (AREA)
Description
第１図及び第２図は本考案の一実施例を示すも
ので第１図はブロツク図、第２図は第１図中の各
部特性を示すタイムチヤートである。また、第３
図は従来例を示す第１図相当図、第４図は第３図
中の各部特性を示すタイムチヤートである。
図中、１は整流回路、２はコンデンサ、３はイ
ンバータ主回路、４は周波数設定器、６は周波数
制御回路、７は波形整形回路、８は負荷、９は交
流電動機、１１は瞬時停電対策回路を示す。
1 and 2 show an embodiment of the present invention, with FIG. 1 being a block diagram and FIG. 2 being a time chart showing the characteristics of each part in FIG. Also, the third
This figure is a diagram corresponding to FIG. 1 showing a conventional example, and FIG. 4 is a time chart showing characteristics of each part in FIG. 3. In the figure, 1 is a rectifier circuit, 2 is a capacitor, 3 is an inverter main circuit, 4 is a frequency setting device, 6 is a frequency control circuit, 7 is a waveform shaping circuit, 8 is a load, 9 is an AC motor, and 11 is a countermeasure for instantaneous power outages. Shows the circuit.
Claims (1)
られ出力周波数の基準となる基準信号を発生する
ための周波数制御回路をＰＬＬ回路により構成し
て成るインバータ装置において、瞬時停電が発生
して復電した後に前記交流電動機の回転数を検出
して前記周波数制御回路から上記検出回転数に相
当するインバータ出力周波数に対応した基準信号
が出力されるようにその周波数制御回路を制御す
ると共に前記復電後に所定の遅れ時間が経過する
までの期間前記周波数制御回路の出力を拘束する
ための拘束信号を出力する瞬時停電対策回路を設
けたことを特徴とするインバータ装置。 An instantaneous power outage occurred in an inverter device that was installed to control the variable speed operation of an AC motor and was configured with a PLL circuit as a frequency control circuit for generating a reference signal that serves as a reference for the output frequency, and the power was restored. Afterwards, the rotational speed of the AC motor is detected and the frequency control circuit is controlled so that a reference signal corresponding to the inverter output frequency corresponding to the detected rotational speed is outputted from the frequency control circuit, and a predetermined signal is set after the power is restored. An inverter device comprising an instantaneous power outage countermeasure circuit that outputs a restraint signal for restraining the output of the frequency control circuit for a period until the delay time elapses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8168585U JPS61199196U (en) | 1985-05-30 | 1985-05-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8168585U JPS61199196U (en) | 1985-05-30 | 1985-05-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61199196U true JPS61199196U (en) | 1986-12-12 |
Family
ID=30628698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8168585U Pending JPS61199196U (en) | 1985-05-30 | 1985-05-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61199196U (en) |
-
1985
- 1985-05-30 JP JP8168585U patent/JPS61199196U/ja active Pending
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