JPS6119940B2 - - Google Patents

Info

Publication number
JPS6119940B2
JPS6119940B2 JP13027080A JP13027080A JPS6119940B2 JP S6119940 B2 JPS6119940 B2 JP S6119940B2 JP 13027080 A JP13027080 A JP 13027080A JP 13027080 A JP13027080 A JP 13027080A JP S6119940 B2 JPS6119940 B2 JP S6119940B2
Authority
JP
Japan
Prior art keywords
circuit
voltage
gap
circuit breaker
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13027080A
Other languages
Japanese (ja)
Other versions
JPS5754875A (en
Inventor
Akira Kato
Shunichi Arakawa
Takakazu Matsunami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Electric Manufacturing Co Ltd
Priority to JP13027080A priority Critical patent/JPS5754875A/en
Publication of JPS5754875A publication Critical patent/JPS5754875A/en
Publication of JPS6119940B2 publication Critical patent/JPS6119940B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/327—Testing of circuit interrupters, switches or circuit-breakers
    • G01R31/333—Testing of the switching capacity of high-voltage circuit-breakers ; Testing of breaking capacity or related variables, e.g. post arc current or transient recovery voltage
    • G01R31/3333—Apparatus, systems or circuits therefor
    • G01R31/3336—Synthetic testing, i.e. with separate current and voltage generators simulating distance fault conditions

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Circuit Breakers, Generators, And Electric Motors (AREA)

Description

【発明の詳細な説明】 本発明は遮断器の遮断性能試験に係り、特にア
ーク時間が0.5サイクルを超えた領域での遮断性
能を検証する遮断器等価試験装置に関する。従来
から遮断器の遮断性能試験においては、アーク時
間が0.5サイクルを超えた領域までの遮断性能を
検証する必要がある。このため、合成等価試験で
は最初の電流零点を通過し確実にアークを延長す
る技術が要求される。一般的には予め別のコンデ
ンサを充電しておき、電流零点でその電荷をリア
クトルまたは抵抗を介し遮断電流に急峻なパルス
電流として重畳し、急速に電流零点を通過させア
ークを更に半波継続させる。しかし特に絶縁回復
特性に優れた遮断器では、上記パルス電流の波形
がアーク延長の成功率に影響するため、前記パル
ス電流を発生させる回路では成功率が極度に低か
つた。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a breaking performance test of a circuit breaker, and more particularly to a circuit breaker equivalence test device for verifying the breaking performance in a region where the arc time exceeds 0.5 cycles. Conventionally, in the breaking performance test of circuit breakers, it is necessary to verify the breaking performance in areas where the arc time exceeds 0.5 cycles. Therefore, in the composite equivalence test, a technique is required to pass through the initial current zero point and reliably extend the arc. Generally, another capacitor is charged in advance, and at the current zero point, the charge is superimposed on the interrupting current as a steep pulse current through a reactor or resistor, and the current zero point is rapidly passed and the arc continues for another half wave. . However, in a circuit breaker with particularly excellent insulation recovery characteristics, the waveform of the pulse current affects the success rate of arc extension, so the success rate of a circuit that generates the pulse current is extremely low.

そこで、理想的な波長は1KHz以上の高周波で
ありり、それが得られるパルス発発生回路の回路
定数を数+μSで切換えることが必要となる。そ
のため、新しい3点ギヤツプ制御方式等が提案さ
れている。
Therefore, the ideal wavelength is a high frequency of 1 KHz or more, and it is necessary to change the circuit constant of the pulse generation circuit to obtain this wavelength by several + μS. Therefore, new three-point gap control systems and the like have been proposed.

理想的な重畳パルス電流波形を得るにはパルス
発生回路を複合形にする必要がある。即ち、零点
に近づいた遮断電流に重畳させるる同極のパルス
電流は、できるだけピーク値を大きく、且つその
電流変化率が負(di/dt<0)の時間帯域で、特
に急速に逆極性にすることで供試遮断器CBtの遮
断能力以上のdi/dtで電流零点を通過させる。し
かし、その次の正半波(第3波目)はその立ち上
りに再度零点を通過することでアーク延長失敗と
ならぬようできる限りピーク値を小さくしなけれ
ばならない。即ち、アーク延長パルス電流波形を
第1波のピーク値を大きくし、第2波への電流変
化率di/dtを大きくして、且つ第2波の波尾をに
ぶらせ第3波高値を0にすることが要請される。
To obtain an ideal superimposed pulse current waveform, it is necessary to make the pulse generation circuit a composite type. In other words, the pulse current of the same polarity to be superimposed on the interrupting current that approaches the zero point has a peak value as large as possible, and the current change rate is negative (di/dt<0) in a time band where the current changes rapidly to the opposite polarity. By doing so, the current passes through the zero point with di/dt that is greater than the breaking capacity of the test circuit breaker CBt. However, the peak value of the next positive half wave (third wave) must be made as small as possible to avoid failure in arc extension due to passing through the zero point again at the rising edge. That is, in the arc extension pulse current waveform, the peak value of the first wave is increased, the current change rate di/dt to the second wave is increased, and the wave tail of the second wave is blunted to increase the third wave peak value. It is requested that it be set to 0.

このため、パルス発生回路の回路定数を短時間
で変更して上記の要請を満足させることが行なわ
れているが、前記回路定数を途中で変更するのに
タイマーを用いた3点ギヤツプ制御方式で行なつ
ている。しかし、交流電圧のピーク瞬時で放電さ
せるため10μSのオーダーで確実にギヤツプ放電
制御を行なうことは従来のタイマーを使用するも
のでは困難であつた。
For this reason, the circuit constants of the pulse generation circuit are changed in a short period of time to satisfy the above requirements, but a three-point gap control method using a timer is used to change the circuit constants midway. is being carried out. However, it has been difficult to perform gap discharge control reliably on the order of 10 μS in order to discharge at the moment of the peak of the AC voltage using a conventional timer.

本発明の目的は上記の欠点に鑑み、10μSのオ
ーダーで確実にギヤツプ放電制御を行なうことが
できる遮断器等価試験装置を提供するにある。
SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks, an object of the present invention is to provide a circuit breaker equivalence test device that can reliably perform gap discharge control on the order of 10 μS.

従つて、本発明は供試遮断器に流れる車断電流
の零点近傍で該遮断電流に重畳してアークを延長
させるためのパルス電流を発生させるアーク延長
ルス発生回路を有すする遮断器等価試験装置にお
いて、前記アーク延長パルス発生回路は回路電圧
を検出することにより放電制御される回路定数切
換用3点ギヤツプを有し、特にそのうちの所定の
3点ギヤツプをトリガーする信号を前記アーク延
長パルス発生回路の電源となる充電コンデンサの
電圧が反転したことを検知する逆電圧阻止ダイオ
ードと、該逆電圧阻止ダイオードの電圧値が所定
値以上になつたことで抵抗が減少する非直線抵抗
素子を介して前記充電コンデンサの一端から得る
ように接続構成されていることを特徴とする遮断
器等価試験装置を提供しようとするもので、以下
実施例を用いて説明する。
Therefore, the present invention provides a circuit breaker equivalence test having an arc extension pulse generation circuit that generates a pulse current to extend the arc by superimposing it on the breaking current near the zero point of the breaking current flowing through the test circuit breaker. In the apparatus, the arc extension pulse generation circuit has a three-point gap for switching circuit constants whose discharge is controlled by detecting a circuit voltage, and in particular, a signal that triggers a predetermined three-point gap among them is used to generate the arc extension pulse. Through a reverse voltage blocking diode that detects when the voltage of the charging capacitor that is the power source of the circuit is reversed, and a nonlinear resistance element whose resistance decreases when the voltage value of the reverse voltage blocking diode exceeds a predetermined value. The purpose of this invention is to provide a circuit breaker equivalence testing device characterized in that it is configured to be connected to one end of the charging capacitor, and will be described below using examples.

第1図は本発明に係る遮断器等価試験装置の一
実施例を示し、同図において、A部は充電回路、
B部はアーク延長パルス発生回路、C部はワイル
回路、D部は電流源回路である。
FIG. 1 shows an embodiment of the circuit breaker equivalence test device according to the present invention, in which part A is a charging circuit,
Part B is an arc extension pulse generation circuit, part C is a Weyl circuit, and part D is a current source circuit.

まずA部の充電回路の構成については、電圧源
12に整流素子14と抵抗16が直列に接続され
ている。
First, regarding the configuration of the charging circuit in section A, a rectifying element 14 and a resistor 16 are connected in series to a voltage source 12.

次にB部のアーク延長パルス発生回路の構成に
ついては、前記充電回路A部で充電されるコンデ
ンサC1の一端にリアクトルL1を介してギヤツプ
(放電ギヤツプ)G1が接続され、また前記コンデ
ンサC1の一端に抵抗R1を介してギヤツプG2が接
続され、このギヤツプG2の他端は前記リアクト
ルL1とギヤツプG1との接続点に接続されてい
る。また、コンデンサC1の一端には逆電圧阻止
ダイオードSDと電圧値が所定値以上になつたこ
とで抵抗が減少する非直線抵抗素子たとえばツエ
ナー特性素子ZDを介してギヤツプG3のトリガー
電極が接続されている。また抵抗R1とギヤツプ
G2の接続点はコンデンサC2と低抗R2を介してコ
ンデンサC1の他端に接続されている。コンデン
サC2と並列にコンデンサC3とリアクトルL3とギ
ヤツプG3とを直列接続したものが接続されてい
る。コンデンサC3とリアクトルL3との接続点に
は抵抗R3,R′3を介してギヤツプG2のトリガー電
極に接続されている。
Next, regarding the configuration of the arc extension pulse generation circuit in part B , a gap (discharge gap) G1 is connected to one end of the capacitor C1 charged in the charging circuit part A via a reactor L1, and A gap G2 is connected to one end of C1 via a resistor R1 , and the other end of this gap G2 is connected to the connection point between the reactor L1 and the gap G1 . In addition, the trigger electrode of the gap G 3 is connected to one end of the capacitor C 1 via a reverse voltage blocking diode SD and a non-linear resistance element, such as a Zener characteristic element ZD, whose resistance decreases when the voltage value exceeds a predetermined value. has been done. Also resistor R 1 and gap
The connection point of G 2 is connected to the other end of capacitor C 1 through capacitor C 2 and low resistance R 2 . A series connection of a capacitor C3 , a reactor L3 , and a gap G3 is connected in parallel with the capacitor C2 . The connection point between capacitor C 3 and reactor L 3 is connected to the trigger electrode of gap G 2 via resistors R 3 and R′ 3 .

またC部のワイル回路の構成については、アー
ク延長パルス発生回路B部のギヤツプG1の他端
に線路のリアクタンスL2、第1の補助遮断器CB1
および供試遮断器CBtが直列接続され、この供試
遮断器CBtの他端は前記コンデンサC1の他端に接
続されている。供試遮断器CBtと補助遮断器CB1
の接続点には第2の補助遮断器CB2を介して電圧
源回路Eに接続されている。
Regarding the configuration of the Weyl circuit in section C, the line reactance L 2 is connected to the other end of the gap G 1 in section B of the arc extension pulse generation circuit, and the first auxiliary circuit breaker CB 1
and a test circuit breaker CBt are connected in series, and the other end of the test circuit breaker CBt is connected to the other end of the capacitor C1 . Test circuit breaker CBt and auxiliary circuit breaker CB 1
The connection point is connected to the voltage source circuit E via the second auxiliary circuit breaker CB2 .

またD部の電流源回路の構成については発電機
などの電流源Gの両端間にインダクタンスL0、
抵抗R0、コンデンサC0および第3の補助遮断器
CB3が直列に接続されている。インダクタンスL0
と抵抗R0の接続点はギヤツプG1の他端に接続さ
れ、また補助遮断器CB3と電流源Gとの接続点は
コンデンサC1の他端に接続されている。
Regarding the configuration of the current source circuit in section D, there is an inductance L 0 between both ends of the current source G such as a generator.
Resistor R 0 , capacitor C 0 and third auxiliary circuit breaker
CB 3 are connected in series. Inductance L 0
The connection point between the auxiliary circuit breaker CB 3 and the current source G is connected to the other end of the capacitor C 1 .

次に本実施例の動作について以下説明する。予
め所定の電圧まで電圧源12によりりコンデンサ
C1及びC2を充電しておき、供試遮断器CBtを開極
後第2図に示すような電流I1の最初の電流零点O1
直前でギヤツプG1をアーク延長指令によりトリ
ガーすると、コンデンサC1―リアクトルL1―リ
アクトルL2の直列回路で決定される第3図Bで
示される電流(B部のアーク延長パルス発生回路
から発生回路からリアクトルL2を介して供給さ
れる電流)I2が流れる。第3図Aは第2図のP部
(O1点符近)の拡大図である。次にコンデンサC1
の電圧極性がほぼ完全に反転した時点(TμS
後)にギヤツプG2がトリガーすると、アーク延
長パルス発生回路B部からリアクトルL2を介し
て供給される電流I′2はコンデンサC1―抵抗R1―
リアクトルL2の経路で決定される波形になる。
そして第3図Cに示すような波形の電流IT(=
I1+I2)はIT(=I1+I′2)となつて供試遮断器CBt
に流れる。
Next, the operation of this embodiment will be explained below. The voltage source 12 connects the capacitor to a predetermined voltage in advance.
C 1 and C 2 are charged, and after opening the test circuit breaker CBt, the first current zero point O 1 of the current I 1 as shown in Fig. 2 is reached.
When the gap G 1 is triggered by the arc extension command immediately before, the current shown in Figure 3B determined by the series circuit of capacitor C 1 - reactor L 1 - reactor L 2 (generated from the arc extension pulse generation circuit in section B) A current) I 2 supplied from the circuit through the reactor L 2 flows. FIG. 3A is an enlarged view of section P (near the O1 point) in FIG. 2. Then capacitor C 1
The point at which the voltage polarity of is almost completely reversed (TμS
When the gap G 2 is triggered in (after), the current I' 2 supplied from the arc extension pulse generation circuit B section through the reactor L 2 is transferred to the capacitor C 1 - resistor R 1 -
The waveform is determined by the path of reactor L2 .
Then, the current I T (=
I 1 + I 2 ) becomes I T (=I 1 + I′ 2 ), and the test circuit breaker CBt
flows to

ところでギヤツプG2をトリガーするTμS時
点は、コンデンサC1の電圧Vの極性が完全に反
転し、かつ電圧がギヤツプG2の閃絡に十分な電
圧に立上がつた最大値近傍が望ましい。
By the way, the time TμS at which the gap G2 is triggered is preferably near the maximum value at which the polarity of the voltage V of the capacitor C1 is completely reversed and the voltage has risen to a voltage sufficient to cause a flashover of the gap G2 .

ギヤツプG2のトリガー信号の電源であるコン
デンサC2はコンデンサC1と共にあらかじめ充電
される。ギヤツプG3をトリガーすると、先ずコ
ンデンンサC2ーコンデンサC3ーリアクトルL3の
回路で共振し、コンデンサC3による電圧で抵抗
R3及びR′3を介しギヤツプG2をトリガーすること
がでる。ギヤツプG2のトリガー(阻ち、G3のト
ガー)をギヤツプG1のトリガー(アーク延長)
よりTμS遅らすには、タイマー回路をギヤツプ
G1の指令と共にスタートさせ所定時限でギヤツ
プG3をトリガーすることが考えられるが、その
同期が困難である。そこで本実施例では、コンデ
ンサC1の電圧が反転したことを逆電圧阻止ダイ
オードSDにより検知し、この逆電圧阻止ダイオ
ードSDの電圧値が所定値以上になつたことで抵
抗の減少する非直線抵抗体、たとえばツエナー特
性素子ZDをギヤツプG3のトリガー電極に結ぶこ
とによりギヤツプG3を確実にギヤツプG1の指令
よりTμS後にトリガーしている。
Capacitor C 2, which is the power source for the trigger signal of gap G 2 , is precharged together with capacitor C 1 . When the gap G 3 is triggered, the circuit consisting of capacitor C 2 - capacitor C 3 - reactor L 3 resonates, and the voltage generated by capacitor C 3 causes resistance.
Gap G 2 can be triggered via R 3 and R′ 3 . Gap G 2 trigger (blocking, G 3 toggle), Gap G 1 trigger (arc extension)
To delay more than TμS, gap the timer circuit.
It is conceivable to start with the command of G 1 and trigger gap G 3 at a predetermined time limit, but synchronization is difficult. Therefore, in this embodiment, the reverse voltage blocking diode SD detects that the voltage of the capacitor C1 is reversed, and when the voltage value of the reverse voltage blocking diode SD exceeds a predetermined value, a nonlinear resistor whose resistance decreases is activated. By connecting a body, for example, a Zener characteristic element ZD, to the trigger electrode of the gap G3 , the gap G3 is reliably triggered TμS after the command of the gap G1 .

本実施例によれば、アーク延長パルス発生回路
B部内の回路定数切換用3点ギヤツプG2,G3の
制御を逆電圧阻止ダイオーードSDを用いた回路
電圧検出方式とすることにより確実に行なわせ、
所期のパルス電流波形(第1波のピーク値を大き
くし、第2波への電流変化率di/dtを大きくし
て、かつ第2波の波尾を鈍らせ、第3波波高値を
零にする)を得ることができる。
According to this embodiment, the three-point gaps G 2 and G 3 for switching circuit constants in the arc extension pulse generation circuit B section are reliably controlled by using a circuit voltage detection method using a reverse voltage blocking diode SD. ,
Intended pulse current waveform (increase the peak value of the first wave, increase the current change rate di/dt to the second wave, blunt the tail of the second wave, and increase the peak value of the third wave) ) can be obtained.

以上の説明から明らかなように本発明によれ
ば、回路電圧を検出することによつて、アーク延
長パルス発生回路の定数切換用3点ギヤツプ
G2,G3の制御をすることにより、10μSのオー
ダーで確実にギヤツプ放電制御を行なうことがで
き、前述した所期のパルス電流波形を得ることが
できる。
As is clear from the above description, according to the present invention, by detecting the circuit voltage, the three-point gap for constant switching of the arc extension pulse generation circuit is
By controlling G 2 and G 3 , gap discharge control can be performed reliably on the order of 10 μS, and the desired pulse current waveform described above can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る遮断器等価試験装置の一
実施例を示す回路図、第2図は第1図の供試遮断
器を開極当初に流れる電流波形図、第3図Aは第
2図のP部の拡大図、第3図Bは第1図のアーク
延長パルス発生回路からリアクトルL2を介して
供給される電流波形図、第3図Cは第1図の供試
遮断器CBtを流れる電流波形図である。 C1〜C3はコンデンサ、CBtは供試遮断器、G1
〜G3はギヤツプ、L1及びL3はリアクトル、L2は
試験線路の漂遊リアクタンス、R1〜R3は抵抗で
ある。
Fig. 1 is a circuit diagram showing an embodiment of the circuit breaker equivalence test device according to the present invention, Fig. 2 is a current waveform diagram that flows when the test circuit breaker in Fig. 1 is first opened, and Fig. 3 Figure 3B is an enlarged view of section P in Figure 2, Figure 3B is a current waveform diagram supplied from the arc extension pulse generation circuit in Figure 1 via reactor L2 , Figure 3C is the test circuit breaker in Figure 1. FIG. 3 is a current waveform diagram flowing through CBt. C 1 to C 3 are capacitors, CBt is the test circuit breaker, G 1
~ G3 is the gap, L1 and L3 are the reactors, L2 is the stray reactance of the test line, and R1 to R3 are the resistances.

Claims (1)

【特許請求の範囲】[Claims] 1 供試遮断器に流れる遮断電流の零点近傍で該
遮断電流に重畳してアークを延長させるためのパ
ルス電流を発生させるアーク延長パルス発生回路
を有する遮断器等価試験装置において、前記アー
ク延長パルス発生回路は回路電圧を検出すること
により放電制御される回路定数切換用3点ギヤツ
プを有し、特にそのうちの所定の3点ギヤツプを
トリガーする信号を前記アーク延長パルス発生回
路の電源となる充電コンデンサの電圧が反転した
ことを検知する逆電圧阻止ダイオードと、該逆電
圧阻止ダイオードの電圧値が所定値以上になつた
ことで抵抗が減少する非直線抵抗素子を介して前
記充電コデンサの一端から得るように接続構成さ
れていることを特徴とする遮断器等価試験装置。
1. In a circuit breaker equivalence test device having an arc extension pulse generation circuit that generates a pulse current to extend the arc by superimposing it on the interrupting current near the zero point of the interrupting current flowing through the test circuit breaker, the arc extension pulse generation The circuit has a three-point gap for circuit constant switching whose discharge is controlled by detecting the circuit voltage, and in particular, a signal that triggers a predetermined three-point gap is applied to a charging capacitor that serves as a power source for the arc extension pulse generation circuit. The voltage is obtained from one end of the charging capacitor through a reverse voltage blocking diode that detects that the voltage is reversed, and a nonlinear resistance element whose resistance decreases when the voltage value of the reverse voltage blocking diode exceeds a predetermined value. A circuit breaker equivalence test device characterized in that it is configured to be connected to.
JP13027080A 1980-09-19 1980-09-19 Equivalent testing device for circuit breaker Granted JPS5754875A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13027080A JPS5754875A (en) 1980-09-19 1980-09-19 Equivalent testing device for circuit breaker

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13027080A JPS5754875A (en) 1980-09-19 1980-09-19 Equivalent testing device for circuit breaker

Publications (2)

Publication Number Publication Date
JPS5754875A JPS5754875A (en) 1982-04-01
JPS6119940B2 true JPS6119940B2 (en) 1986-05-20

Family

ID=15030272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13027080A Granted JPS5754875A (en) 1980-09-19 1980-09-19 Equivalent testing device for circuit breaker

Country Status (1)

Country Link
JP (1) JPS5754875A (en)

Also Published As

Publication number Publication date
JPS5754875A (en) 1982-04-01

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