JPS6120823B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electric timepiece that generates a reference signal of a predetermined frequency using the natural vibration of a crystal oscillator terminal, and performs a timekeeping operation based on this reference signal.

Electric clocks equipped with a reference signal source having a crystal oscillator have already become commonplace, but the frequency of the reference signal obtained from a normal reference signal source fluctuates, especially due to changes in ambient humidity. This causes the accuracy of the clock to decrease.

SUMMARY OF THE INVENTION An object of the present invention is to provide an electric timepiece that has a reference signal generation source whose oscillation frequency fluctuates very little due to changes in external conditions, and can therefore stably maintain high accuracy.

In the past, when moisture entered a mechanical watch, the components of the mechanical timekeeping mechanism of the watch could deteriorate over time, deteriorating its properties as a watch, but extremely large amounts of water could Unless otherwise specified, no serious situation such as a stoppage of timekeeping operation would have occurred. In recent years, with the advent of crystal oscillation type high-precision electric clocks, timekeeping accuracy has improved dramatically, and in particular, the mechanisms that influence timekeeping accuracy have been solidified by adopting an electric timekeeping unit signal creation mechanism. The accuracy of the time displayed on a clock has come to be considered extremely reliable. However, if a crystal clock is not made with care, its timekeeping may be completely disrupted due to trivial reasons, and even though the temporal accuracy is very good, the reliability of the time is lower than that of traditional mechanical clocks. Situations like this can also occur. for example,
An electromechanical transducer for moving a mechanical pointer by means of an electrically generated time reference signal with precise time interval and phase can perform translational or may deviate from normal operation due to rotationally applied mechanical acceleration disturbances. By shortening the time span of the converter's state change and reducing the ratio of the time it takes to remain in a stable state against external disturbances in the rest state, it is possible to prevent malfunctions in a stochastic manner. By increasing the potential of the change state to make it insensitive to weak disturbances, in the unfortunate event that the converter malfunctions due to disturbance, it will be detected and this error amount will be corrected. etc. must be taken into consideration when designing. Measures must also be taken to prevent batteries from becoming disconnected for a short period of time due to external disturbances. As battery impedance increases at low temperatures, it is also necessary to connect a capacitor in parallel to maintain low power source impedance and ensure crystal oscillation and converter operation. The adjustment mechanism of a watch must be sufficiently resistant to acceleration disturbances and moisture; if the watch is left standing still in dry air, it will keep the time accurately, but if you put it on your wrist, it will start moving on its own and go out of order. It may end up being put away. Most oscillator circuits have high impedance to extend battery life, and even a small amount of moisture absorption could shift the oscillator's operating point and cause it to stop oscillating. Even if the bias does not go out of order, the load impedance of the oscillation circuit becomes too low and the oscillation conditions are no longer satisfied. To prevent this, at least cover part or all of the oscillation circuit including the bias setting section with an insulator, or make it an integrated circuit, to at least eliminate the bias deviation or reduce the load. It is possible to prevent the crystal from becoming heavier or from lowering the Q value of the crystal resonant circuit. In other words, the high precision of a quartz watch cannot be applied to the accuracy of timekeeping unless it is designed and assembled based on sufficient inspection. It is possible to obtain a highly reliable watch that takes advantage of its characteristics.

An embodiment of the present invention will be described below based on the drawings.

In the case of this electric clock, basically, a reference signal oscillation source 11, a frequency dividing circuit 12, a frequency adjustment device 13 that controls the frequency division ratio of the frequency dividing circuit 12, and a frequency dividing circuit 12
an electrical timekeeping device 14 and a mechanical timekeeping device 15 that measure time in response to a timekeeping unit signal created by the above, a display device 16 that displays the time held by the mechanical timekeeping device;
It is comprised of an operating mechanism 17 that operates each of the electrical and mechanical timekeeping devices, and an electrical control device 18 that controls the electrical timekeeping device 14 and the mechanical timekeeping device 15 using signals from the operating mechanism.

The frequency adjustment device 13 includes an operation section 13a, a frequency division ratio control circuit 13b, and an EXCLUSIVE-OR gate 1.
3c, and a part of the signal from the frequency dividing circuit 12 is sent to each circuit section as a clock pulse signal φCl ₁₂ via a clock pulse generating circuit.

The mechanical timing device 15 includes a drive pulse forming circuit 15a, a drive mechanism 15b, and a wheel train 15c, and the display device 16 includes an ordinary mechanical pointer 16a. The operating mechanism 17 is R
Switch input circuit 30, _S0 switch circuit 21, pulse shaping circuit 22S, _M0 switch input circuit 2
0, noise prevention circuit 32, pulse shaping circuit 22M
The electrical control device 18 is composed of S ₀
Switch input control circuit 23M, holding time control circuit 24, memory counting circuit 25, count content discrimination circuit 2
6, a coincidence detection circuit 29, and a set command circuit 28, and the LED display section 19 is controlled by a signal from the count content discrimination circuit 26.

The reference signal oscillation source 11 is a reference signal oscillator including a vibrator such as a crystal oscillator tuning fork or a vibrator, and its frequency is divided down to a low frequency by a frequency dividing circuit 12. In a conventional crystal electric timepiece, a mechanical timekeeping device 15 is driven by the low frequency signal, and the time is displayed using a pointer 16a.

The electric timepiece of the present invention is provided with an operating mechanism 17, an electric timekeeping device 14, and an electric control device 18, and the operation thereof will be described in detail below.

The 1 Hz signal from the frequency dividing circuit 12 passes through the holding time control circuit 24 and is counted by the electric timer 14, and the counted value is stored in the storage counter 25. During normal operation of the watch, the contents of the electrical timekeeping device 14 and the memory counting circuit 25 match, the coincidence detection circuit 29 detects this, and the holding time control circuit 24 sends out a drive pulse to drive the pointer. . In other words, during normal watch operation, this electric watch hands 16.
The M ₀ switch is configured to automatically operate each time the second hand in a moves to the 0 second position by a cam mechanism interlocking with the second hand shaft. and this
When the _M0 switch is turned on, the time held by the mechanical timekeeping device 15 is made to match the time held by the electrical timekeeping device 14, so that no difference occurs between the respective time systems. When the S ₀ switch operates at 0 seconds of the external standard time, if the time held by the electric clock is between 0 seconds and 29 seconds, it will be ``advanced'' compared to the standard time by the number of seconds between. , the second hand stops at the same position, moves steadily after the number of seconds it has advanced, and when the held time is "30 seconds to 59 seconds", the second hand is compared with the standard time by the complement of that second. The second hand is fast-forwarded to the 0 second position, and then driven in a steady manner to match the standard time.

In this case, when the _S0 switch is operated, a synchronizing pulse is created in the pulse shaping circuit 22S, and this signal is
It is transmitted to the holding time control circuit 24 via the _S0 switch input control circuit 23S. Here, the time stored in the memory counting circuit 25 is "0 seconds to 29 seconds".
The count content discrimination circuit 26 determines whether the count is “seconds” or “30 seconds to 59 seconds”.
Upon receiving the signal discriminated in step 1, the electric timer 14, memory counting circuit 25, and drive pulse forming circuit 28 receive either a set signal, a reset signal, a 32Hz signal, a 1Hz signal, or a stop command signal, depending on the content of the discrimination. to send instantaneously or continuously. At this time, the error between the external standard time and the time held by the electric timer 14 is measured and stored in the electric timer 14 or the memory counting circuit 25, and when synchronization with the standard time is achieved, When the respective counters match, a signal detected by the match detection circuit 29 is transmitted to the _S0 switch input control circuit 23S, and from there a command signal is transmitted to the holding time control circuit 14 to complete the time adjustment operation. be done.

The functional configuration of the S ₀ switch is also the same when the M ₀ switch synchronizes the times held by the mechanical time measurement device 15 and the electrical time measurement device 14 .

In this way, with this electric watch, the time can be adjusted with extremely high precision just by pressing the S ₀ switch once at 0 seconds.

In addition, the R switch input circuit 30 can be used in a hurry, etc.
This is used to stop the second hand at a time other than 0 seconds of the standard time, and then start the second hand to normal operation according to the standard time, and supplements the function of the _S0 switch.

Figure 2 shows the actual electric clock shown in Figure 1.
One embodiment of the IC circuit will be described in detail below with reference to FIG.

In FIG. 2, the reference signal generation source 11 includes a crystal resonator 53 connected between terminals 51 and 52;
A coupling capacitor Cc inserted between the terminal 51 and the inverter 54, and a high resistance R _N (for example,
30MΩ). Note that numerals 55 and 56 are
A MOS transistor is shown that acts as a resistance element for supplying a predetermined operating current to the inverter 54. These elements, except for the crystal resonator 53, are incorporated into a single C/MOS integrated circuit.

In the reference signal generation source 11 having such a configuration, even if the humidity changes widely, the high resistance R is maintained due to the integrally molded coupling capacitor.
Changes in the bias applied to the inverter 54 by _N are extremely small, resulting in good frequency stability of the oscillation output. Also coupling capacitor
There is also the advantage that the stray capacitance generated by providing Cc acts as an oscillation capacitor for the crystal resonator.

J ₁₂ , J ₆ , J ₃ , and J ₁₅ are frequency adjustment terminals, and terminal R is connected to a reuse switch (not shown).
Used to stop the second hand at any desired position.

In other words, terminal R is the negative side of the power supply in the normally open state.
Connected to Vss, and connected to the main plate of the watch (positive side of power supply V ^DD ) only when stopping the second hand.

The terminal _s0 is connected to the reuse switch, and connected to the positive side of the power supply ^VDD only when you want to set zero seconds, and the R
The terminal prevents zero-second setting when the clock is stopped. That is, the zero second setting is carried out by rapidly forwarding or stopping the second hand.

Terminal M ₀ is an input terminal for synchronization, and is connected to the main plate at least once with the second hand pointing to 0 seconds. It may be connected every 0 seconds of the second hand, or it may be connected to the main plate only once at the 0 second position of the second hand after the battery is manually set in the watch. As a result, the relative relationship between the position of the second hand of the watch and the electrically measured second is stored in the watch, synchronization calculations are performed within the IC, and the two are synchronized by fast forwarding or stopping the second hand.
In a synchronized state, the position of the second hand of the clock and the second of the electronic timer coincide. Synchronization is achieved by setting the second hand to electronic timekeeping.

The LED display section 19 is provided to indicate that the clock is not stopped due to a malfunction when the second hand is stopped to set the clock to 0 seconds, and it blinks in synchronization with the second pulse.

Furthermore, the LED output also serves as an input terminal, and S ₀
By connecting the terminal and the LED terminal and grounding them to the ground plane (the positive side of the power supply V ^DD ), the electric circuit sets the internal state to "0". The internal state “0” means that the seconds in the electrical time are “0”.
Then, the pulse motor-driven phase determining device (corresponding to the flip-flop FF24) is set to an even second phase (corresponding to 0 seconds of the second hand).

QA and QB are alternating pulse drive signals for the pulse motor, and the potential difference between the drive signals QA and QB changes sign every second and is a narrow pulse lasting 1/64 second.

Now, when a 32.768 (=2 ¹⁵ ) Hz crystal oscillator 53 is connected between the terminals 51 and 52, the oscillation frequency of 32,768 Hz is transmitted to the frequency dividing circuit array 12a of the flip-flops FF ₁ to FF ₁₀ and the frequency dividing circuit array 12a of the flip-flops FF ₁₁ to _{FF 15} . The frequency is divided to 1 Hz by the reset frequency divider circuit array 12b.

The above flip-flops FF ₁ to FF ₁₀ simply divide the input frequency, but flip-flops FF ₁₁ to _{FF 15} can adjust the phase of the output signal by applying a reset, and the time measurement unit of the clock is
The period of the 64Hz signal that is the output of FF ₁₀ , that is, 16m
SEC (=1/64 second).

Since all flip-flops FF in this embodiment change their outputs in synchronization with the rising edge of the input signal, the flip-flop FF changes its output during the pulse train of _the output pulse _Q10 of flip-flop FF10.
Output pulse of FF ₂₂ Q ₂₂ and said flip-flop
A clock pulse φcl ₁₂ created from the output pulse Q ₁₀ of FF ₁₀ is located.

The clock pulse φcl ₁₂ is the IC of this example circuit.
IC was created to ensure the operation of
It prevents the electronic time from becoming incorrect due to noise during various internal calculation processes, and has little to do with the basic operation of the IC. The frequency-divided outputs include an output signal P ₁ of 1 Hz with a width of 1/64 seconds and an output signal P ₃₂ of 32 Hz with a width of 1/64 seconds.

Feedback is applied from the frequency dividing circuit 12 to the EXCLUSIVE-OR gate 13c via the frequency dividing ratio control circuit 13b.

The output signal P _Mc from the hold time control circuit 24 is input to the flip-flop FF ₂₄ , and the frequency is divided by 1/2. Since the output signal Q ₂₄ of the flip-flop FF ₂₄ is alternately inverted every time the output signal PM of the holding time control circuit 24 is input, it can be synchronized with the motor drive phase and used in place of the motor phase. Therefore, by combining the output signal Q ₂₄ of the flip-flop FF ₂₄ with the output signal P _Mc of the holding time control circuit 24, the alternating pulse drive signals QA and QB of the pulse motor can be created.

That is, the pulse motor drive signal is obtained as QA=Q ₂₄ ·P _Mc +Q ₂₄ ·P _Mc QB=Q ₂₄ .

The motor is driven by pulse motor drive and signals QA and QB, the time from seconds onward is maintained by a wheel train system 15c directly connected to the motor, and the time is displayed by a hand 16c (hereinafter referred to as a mechanical timekeeping system). ) On the other hand, the timepiece of the present invention has an electrical timekeeping system, and the output signal P _Ec from the holding time control circuit 24 is transmitted to a six-stage flip-flop which is the electrical timekeeping device 14.
It is connected to FF ₁₆ to FF ₂₁ and measures up to 60 seconds. Normally, a 6-stage flip-flop counts up to 64, but when "60", "61", "62", and "63" are detected by the flip-flop FF ₂₃ , the NAND gate 28
It is set to "0" by a, making it sexagesimal.

That is, both the mechanical timekeeping system and the electrical timekeeping system measure time based on the output signal from the control section 24.
In particular, the frequency divider circuit of flip-flops FF ₁₁ to _{FF 15} is a counter directly connected to the frequency divider circuit of flip-flop FF ₁₀ , whereas the frequency divider circuit of flip-flops FF ₁₆ to FF 15 is a counter directly connected to the frequency divider circuit of flip-flop FF 10.
The electrical timekeeping device 14 of the FF ₂₁ is characterized in that it is a timekeeping system that is equal and independent from the mechanical timekeeping device 15.

Next, control will be explained.

When setting the time to 0 seconds, the contents of the electrical timer 14 are read into the memory counting circuit 25 moment by moment, and when the memory counting circuit 25 is temporarily used for control calculations, the stored time as the electrical timer is read. It is a memory element that prevents data from being lost, and is used to store the retained time depending on the situation or to store the corrected time. The counting contents of the electrical timing device 14
The stored counting contents of the _EC2 /memory counting circuit 25 are hereinafter abbreviated as _EC3 .

In steady state, if EC ₂ = 0 to 29 seconds,
The counting contents are such that when EC ₂ =EC ₃ EC ₂ =30 to 59 seconds, the counting contents are set to EC ₃ =0.

Let us now consider the case where the 0 second set signal S ₀ is input.

a When the 0 second set signal is input in the state of EC ₂ = 0 to 29 seconds, the clock is ahead by the count of EC ₂ compared to the standard clock that is the object of observation, so EC ₂ is Just set it to 0 seconds, then EC ₂
Pointer 16a of the mechanical timekeeping device until = EC ₃
A 1 Hz signal is sent to the electrical timekeeping device 14 while the timer is stopped, and when the count content EC ₂ of the electrical timekeeping device becomes equal to the memory count content EC ₃ of the memory counting circuit, the pointer 16a of the mechanical timekeeping device is removed and normal operation begins.

b When the set signal S ₀ is input in a state where EC ₂ = 30 to 59 seconds, the clock is delayed by (60 - EC ₃ ) compared to the standard clock that is the object of observation. In this case, reset EC ₃ to 0 seconds, send a 32Hz signal to the electrical timer 14 and the mechanical timer, and fast-forward both the mechanical and electrical timers until EC ₂ becomes 0 and equal to EC ₃ . At this point, fast forwarding is stopped and normal operation begins.

Through the above-mentioned functional operations, it has become possible to control the advance and lag of the clock.

The above-mentioned control operation becomes meaningful only when the mechanical timekeeping device and the electrical timekeeping system match their respective holding times.

Measuring the coincidence of this held time (in this case, in terms of seconds) is written as "synchronization", and the held time of the mechanical timekeeping system is written as MC ₁ , then the held time of the electrical timekeeping system is written as "synchronization". Actually, the following two methods can be considered for synchronizing the counting contents EC ₂ of the electrical timekeeping device 14.

(i) When adapting a mechanical timekeeping system to an electrical timekeeping system (MC ₁ →EC ₂ ) (ii) When adapting an electrical timekeeping system to a mechanical timekeeping system (MC ₁ ←EC ₂ ) MC ₁ If an uncertain electrical timekeeping system is involved, it is more reasonable to take method (i).
It is possible to synchronize MC ₁ and EC ₂ in the same way as the arithmetic control when the 0 second set signal S ₀ is input. In this embodiment, the input terminal _M0 is the input terminal for synchronization. To synchronize manually,
Just input the M ₀ signal when the second hand indicates 0 seconds. This synchronizes MC and EC ₂ unless the converter malfunctions.

Another method is to attach a cam to the second hand gear and automatically input the M ₀ signal at 0 seconds every 60 seconds.

To obtain synchronization using the method (ii) above, it is sufficient to set EC ₂ →“0 ₁ ”Q ₂₄ →0 when MC ₁ =“0”.

Considering the case of synchronization using method (i), (a) When M ₀ 205 is input at EC ₂ = 0 to 29 seconds, M ₀
is entered at the 0 second position of the pointer, so in this case, the mechanical timekeeping system lags behind _the electrical timekeeping system by the value of EC ₂ . A 32Hz fast-forward signal is sent to the mechanical timekeeping device 14 to fast-forward both the mechanical timekeeping system and the electrical timekeeping system, and when EC ₂ =EC ₃ , normal operation is restored.

(b) When inputting the M ₀ signal at EC ₂ = 30 to 59 seconds,
In this case, the mechanical timekeeping system is ahead of the electrical timekeeping system by the value (60 - EC ₂ ), so EC ₃ is reset to 0, and a 1Hz signal is directly sent to the electrical timekeeping device 14. The official timekeeping system is stopped,
When EC ₂ = EC ₃ = 0, the stoppage is canceled and normal operation is resumed.

When both S ₀ and M ₀ are input, fast forwarding sends steps less than 30 seconds at 32Hz, so the operation is completed within 1 second. In order to advance or retard the clock in response to the clock's correction signal, it is necessary to store both the clock's time difference and the held time in some way, and also to perform addition/subtraction operations as a clock. It is necessary to do this without damaging the holding time.

Here, the memory counting circuit 2 which is characteristic in this configuration
5 and _M0 input time gate,
After that, I will explain the specific modifications.

To compare the counting contents EC ₂ of the electrical timing device 14 and the holding time MC ₁ of the mechanical timing system, there is a method for detecting the state of MC ₁ when EC ₂ = 0, and a method for counting EC ₂ when MC ₁ = 0. One possible method is to detect the state. In the former, it is necessary to know the state of the mechanical counter in sign and value at any state of MC ₁ and at EC ₂ =0. It is necessary to measure both the mechanical quantities of cosign and the presence or absence of a difference.
Therefore, regardless of whether there is a deviation or not, it is not easy to measure the amount of deviation. In the latter case, at MC ₁ = 0
If the state of EC ₂ , that is, the time of electrical time measurement, is memorized by some means, subsequent synchronization operations can be determined with a single input of information, without having to take the trouble to calculate the deviation between MC ₁ and EC ₂ .

That is, in the former case, it is necessary to detect the deviation and sign of the pointer holding time as a mechanical quantity at any time, whereas in the latter case, it is only necessary to obtain a signal at 0 seconds of the pointer.
In the latter case, assuming that the value of EC ₂ at MC ₁ = 0 is known, in order to synchronize MC ₁ and EC ₂ , it is necessary to memorize the result of correction by calculation and repeat MC ₁ and EC ₂ until the result matches. control.

Memorize the correction amount and simply MC ₁ ,
Fix EC ₂ .

In either case, it is clear that some kind of storage means is required. In this configuration example, the above is used, and a memory counting circuit 25 for time storage is prepared. The counting function of this memory counting circuit relies on the electrical timekeeping device 14, and stores the correction result of the counting content (held time) _EC2 of the device.

In the latter case as well, it is possible to synchronize with a plurality of synchronization signals by storing only the presence or absence of the correction amount and the sign, rather than the result of the correction, in a flip-flop.

Therefore, the memory counting contents of the memory counting circuit 25
EC ₃ coincides with the count content EC ₂ of the constant electric timing device 14, but when EC ₂ = 30 to 59 seconds,
EC ₃ =0. This is because the correction of EC ₂ ensures that when EC ₂ = 30 to 59 seconds, it becomes 60 seconds. At EC ₂ = 0 to 29 seconds,
If you correct it by the number of counts of EC ₂ and make corrections for the elapsed time required for correction, the original value of EC ₂ will be returned, so the value of EC ₂ will be stored in EC ₃ by the correction signal, and EC ₂ itself will be set to 0. The delay of the correction from EC ₂ → EC ₃ in seconds and the control of the mechanical timekeeping system and the electric timekeeping system differ depending on the _S0 input (0 seconds set) and the _M0 input (synchronized input). A mechanism is required to distinguish and store both the S ₀ and M ₀ inputs.

In this configuration example, flip-flops FF37 and FF
38 corresponds to this.

The output signal DET of the coincidence detection circuit 29 is EC ₂ and EC ₃
This is a signal that detects whether or not the this signal
By DET, the S switch input control circuit 23 and the M switch input control circuit 23M are reset and return from the correction state or synchronization state to the steady state.

The signal Qc is a signal for detecting whether the count content of the electrical timekeeping device 14 is between 30 and 59 seconds, and is EC ₂
= 30 to 59 seconds, the logic output is always “1”,
When the time is between EC ₂ -0 and 29 seconds, the logic output is "0".

From the combination logic of the above signals Q ₀ and Q ₃₇ or Q ₃₈ , stop driving the electric time system or mechanical time system, or
Controls whether to perform fast forwarding or both to perform 1Hz forwarding.

Although it has been shown that the above configuration allows both synchronization and 0 second setting, it is necessary to further study the convergence operation in the initial state. i.e. MC ₁ and EC ₂
This is a study on the M ₀ input and the S ₀ input in a state where they do not match.

For example, if MC ₁ = 0 and EC ₂ = 28 seconds, then MC ₁ =
28, synchronized at EC ₂ = 28, MC ₁ = 1 and EC ₂ = 29 seconds
When S ₀ is input, MC ₁ =1 and the second hand stops for 29 seconds. Therefore, MC ₁ is delayed for the first 28 seconds,
There will be an additional 29 seconds delay.

Then, when MC ₁ = 60 seconds after MC ₁ starts moving, EC ₂ = 28 seconds, so the second hand of MC ₁ is fast-forwarded by 28 seconds, and MC ₁ = EC ₂ = 28 seconds. Therefore, in the initial state, it is sufficient to wait until the M ₀ signal is input without inputting S ₀ . If the switch M ₀ contains noise, the noise signal M ₀ will always cause the held time EC ₂ of the electrical timekeeping device 14 and the held time MC ₁ of the mechanical timekeeping system to be out of synchronization. In order to eliminate this, a noise prevention circuit 32 consisting of flip-flops FF ₃₃ and FF ₃₆ is inserted, and when the M ₀ signal is input, the correction control mechanism is insensitive for 16 to 24 seconds even if the M ₀ signal is input. It is a timer circuit that looks like this. Without this noise prevention circuit, the hands of a watch may not converge to the correct time. Also, _S0 input is prohibited.

That is, the S ₀ signal input is a flip-flop
The signal is shaped by the pulse shaping circuit 22S consisting of FF ₃₁ , FF ₃₄ and the NOR gate 22a, and becomes a signal synchronized with the clock pulse φcl _2. Moreover, it is output as a differential signal S↑ synchronized with the leading edge of the S ₀ signal input to the S ₀ switch input control circuit. Set 23S.

Similarly, the _M0 signal is input, and after being converted into a signal lasting 8 to 24 seconds by the noise prevention circuit 32, it is differentiated and sent to the flip-flops FF ₃₂ and FF ₃₅ .
Pulse shaping circuit 2 consisting of NOR gate 22b
2M, the signal becomes a signal synchronized with the clock pulse _φcl12 , and becomes a differential signal M↑, which sets the _M0 switch input control circuit 23. The width of the M ₀ signal is expanded by the noise prevention circuit 32.
It is only extended by the M ₀ signal and does not affect the differential rising differential signal created at the leading edge.

Therefore, control signals U and V are generated from the output signals Q ₃₇ and Q ₃₈ of the flip-flops FF ₃₇ and FF ₃₈ and the output signal Qc of the count content determination circuit 26.

That is, Q ₃₇ = S ₁・Q ₃₈ =M ₁ U=S ₁・Qc+M ₁・Qc V=S ₁・R・M ₁ , and U is fast forward, that is, S ₀ input from 0 to 29 seconds, or 30 to This is the M ₀ input signal of 59 seconds, which is a signal that fast-forwards the holding time MC ₁ of the mechanical timekeeping system. The same signal also fast-forwards the time _EC2 held by the electrical timekeeping device.

Therefore, a logic value of U=0 will send EC ₂ at 1 Hz. Also, V is the holding time MC ₁ of the mechanical timekeeping system.
is a signal sent at 1 Hz, and at a logical value of V = 1,
A read clock pulse is created from the holding time EC ₂ of the electrical timekeeping device to the memory count content EC ₃ of the memory counting circuit, and the signal to send MC ₁ is P _Mc , the signal to send EC ₂ is P _Ec , P ₁ is 1 Hz, Expressing P ₃₂ as a 32Hz signal, P _Mc = P ₁・V+P ₃₂・U P _Ec = P ₁・U+P ₃₂・U, and when EC ₃ = EC ₂ is detected, S ₀ with the DET signal.
The switch input control circuit 23S and _M0 switch input circuit 23M are reset, and the correction or synchronization operation is completed.

In addition, the symbol Q ₁ written on the circuit in Fig. 2
... _Q38 is the output signal of flip-flop _FF1 ... _FF38 , _P1 is the 1Hz signal, P32 is the 32Hz signal, _φcl12 is the clock pulse signal _{SE1 , SE2 is} the output signal of the set command circuit, DET is the coincidence detection Output signal of the circuit, R
is a reset signal, S is a set signal, U and V are signals that control the transmission of 1Hz or 32Hz signals to the mechanical and electrical timekeeping system, P _Mc is a driving control signal to the mechanical timekeeping system, and P _Ec is an electrical signal. Q _c is the output signal of the count content discrimination circuit 26 of the electrical timekeeping system, S↑, M↑ are the pulse shaping circuits 22S, 2, respectively.
2M and M ₁ are symbols representing the output signals of the M ₀ switch input control circuit 23M, respectively, and their time charts are shown in FIGS. 3 to 7.

With this configuration, correction and synchronization can be performed within one second and in one time for correction of even small time delays, synchronization and correction are performed using the same calculation mechanism, and furthermore, the control system No oscillation occurs either. Instead, it requires an electrical timekeeping storage mechanism. Also, from the mechanical timekeeping system, there is only one signal MC ₁ = 0,
Moreover, it is enough to do it only once. Of course, continuous use is also possible.

As described above, according to the present invention, even if the humidity changes widely, the frequency of the reference signal from the reference signal generation source is maintained constant, so that high reliability as a timepiece can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the basic configuration of an electric clock according to the present invention, Fig. 2 is a circuit diagram showing an embodiment of Fig. 1, and Figs. 3 to 7 are time charts of each part of Fig. 2. Figure 3 is a time chart when operating the R switch, Figure 4 is a time chart when 0≦E・C ₂ <30.
Time chart when the S ₀ switch is operated. Figure 5 is a time chart when the S 0 switch is operated when 30≦EC ₂ < 60. Figure 6 is a time chart when the S ₀ switch is operated when 0≦EC ₂ < 30. case time chart,
FIG. 7 is a time chart when the M ₀ switch is operated when 30≦EC ₂ <60. 11... Reference signal generation source, 12... Frequency dividing circuit,
13... Frequency adjustment device, 14... Electric timing device, 15... Mechanical timing device, 17... Operating mechanism, 18... Electric control device.

Claims (1)

[Scope of Claims] 1. An electric clock comprising means for dividing the output signal of a reference signal generation source to create a timekeeping unit signal, and time display means for counting and displaying time based on the timekeeping signal. In the reference signal generation source, a crystal resonator and an oscillation inverter are inserted between an AC coupling capacitor inserted between the crystal resonator and the oscillation inverter, and an output terminal and an input terminal of the oscillation inverter. 1. An electric timepiece comprising a crystal oscillator with a high DC bias resistance, the oscillation inverter and a coupling capacitor being integrated with an insulator. 2. An electric timepiece according to claim 1, characterized in that an oscillation inverter and a coupling capacitor are integrated into the same chip.