JPS6122504B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of Application of the Invention The present invention relates to a device configuration for efficiently counting run lengths used in facsimile encoding. That is, as shown in the explanatory diagram of FIG. 2, the length of time in which the same white and black states continue for two scanning lines is 6 for white, 1 for white, 4 for black, and 4 for white.
This is an attempt to efficiently count white 3, white 6, and so on.

(2) Prior Art Until now, encoding has often been performed using wired logic, but this has many disadvantages when performing advanced processing.

On the other hand, if everything were controlled by a program, this problem would be solved, but there was a problem of insufficient computer time, which often prevented realization.

(3) Purpose of the invention The purpose of the present invention is to solve the above problems,
More specifically, the object is to provide a means for performing only the time-consuming portion of encoding using wiring logic.

(4) General explanation of the invention In conventional program control, there were particularly many problems in terms of time, for example, when encoding two lines at once, or when encoding by focusing on the deviation between two lines. The problem is that the image information for each line is stored in different locations, and as a result, when processed by a general-purpose processing device, the calculations span two bytes, which takes processing time.
In order to solve this problem, a special counting circuit for this purpose is provided as a peripheral device of the general-purpose processing device to realize an economical system.

(5) Examples Hereinafter, the present invention will be explained in detail with reference to examples. FIG. 1 is a block diagram for this purpose. The configuration of the computer, except for the counting circuit 1, is a well-known computer.
That is, the address bus 2, the data bus 3, the photo sensor array 4, and the central processing unit CPU.
5, a program memory (ROM) 6, a data memory (RAM) 7, and a data sending circuit TRAN8.

The image information obtained from the photosensor array 4 is 1
The data is sequentially run-length encoded in byte units under the control of the CPU and memory, and is sent out as data from the sending circuit 8, as is well known.

The center of the present invention is the counting circuit 1, the details of which are shown in FIG.

The 8-bit information of the pre-divided positions of the current scanning line is input to the shift register 11.
Then, the 8-bit information at _the corresponding _position of the next scanning line is set to the shift register 12 via input terminals _E0 to _E7 . On the other hand, information immediately before the corresponding position of each scanning line is stored in the flip-flops 13 and 14 by a method to be described later. However, in the case of the beginning of a scanning line, an appropriate initial value may be set from the input terminals G ₀ and G ₁ .

Now, the information set in shift registers 11 and 12 is compared with the final stage outputs of flip-flops 13 and 14 in exclusive OR circuits 15 and 16. If both match, the output of the inversion circuit 18 is set to "1" via the OR circuit 17. As a result, the OR circuit 20 becomes "1" and causes the pulse of the pulse generating circuit 19 to be outputted via the AND circuit 21.

The output of this AND circuit 21 is first applied to shift registers 11 and 12, and shifted one bit at a time (downward in the figure). It is also added to flip-flops 13 and 14, and sets the final stage outputs of shift registers 11 and 12, respectively, to the flip-flops.

Further, 1 is added to the run length counter 22. Also, 1 is added to the bit counter 23.

The above operations enable the following items. That is, the run length counter 22 counts the number of times the same state continues over two scanning lines. Further, by shifting the shift registers 11 and 12 and updating the flip-flops 13 and 14, the same processing can be performed for the next bit position of the image. In addition, the bit counter 23
By counting the number of times this process has been performed, it is possible to know when the 8 bits set in the shift register have been completed.

Now, a case will be described in which the state of at least one scanning line changes and at least one of the exclusive OR circuits becomes "1" while counting the same state as described above. In this case, since the OR circuit 17 becomes "1", the output of the inverting circuit 18 becomes "0".
Therefore, the output of the pulse generator is inhibited by the AND circuit, and further operation is stopped.

On the other hand, the output of the exclusive OR circuit 17 is the output terminal
Output to _C7 . This information is transmitted to the central processing unit by a look-in (or an interrupt) from the central processing unit. The central processing unit can obtain the run length counting result by reading the run length counter outputs _A0 , _A1 ... _A7 , _B9 , _B1 ... _B7 . Also, the state at that time can be read from C ₀ and C ₁ .

After reading, a central processing unit reset signal is applied from input terminal _F7 . As a result, the run length counter 22 is reset to zero.

Further, the pulse output of the pulse generation circuit 19 is outputted from the AND gate 21 via the delay element 25 and the OR circuit 20 .

As a result, flip-flops 13 and 14 are changed to a new state. Then, the same operations as described above are performed.

Note that if the shift registers 11 and 12 are set and then shifted by 8 bits, it is necessary to set new image data next time. For this reason, when the bit counter 23 reaches a certain value, it can be read from _C6 (or it can be interrupted).
I'll keep it. If this counter counts 8 in cycles, it is not necessary to reset it by _F6 except at the beginning.

Also, flip-flops 13 and 14 retain their previous states one after another, so normally they can be left as they are, but
Especially when making initial settings such as at the beginning of a scan line.
You can input from G ₀ and G ₁ .

Now, the present invention has many variations as described below.

(1) It is possible to process any number of scanning lines (including one), not just two lines at once.

(2) Input terminals D ₀ to _{D 7} , E ₀ to E ₇ , F ₆ , F ₇ , G ₀ ,
G ₁ , output terminals A ₀ -A ₇ , B ₀ -B ₇ , C ₀ , C ₁ can be grouped together so that they can be connected to a bidirectional bus, which is currently known in microcomputer peripheral circuits. C ₆ and C ₇ are also possible, but
It is more advantageous for the system to handle it as an interrupt output.

(3) Well-known so-called DMA (Direct Memory)
Access) function may be used to directly send and receive information to and from the memory unit.

(4) The number of bits of image data handled at one time is 8 due to the structure.
It is not limited to bits, but can be any value.

(6) Summary As described above, according to the configuration of the present invention, program control can be easily realized by performing run-length counting at high speed, which is required in encoding that requires run-length counting. When used in practical applications such as peripheral circuits for microcomputers, the effect is extremely large.

[Brief explanation of the drawing]

FIG. 1 shows an example of the configuration of a processing device including a counting circuit according to the present invention. FIG. 2 is an explanatory diagram of the known run length counting for two lines at once. FIG. 3 shows the configuration of an embodiment of the run length counting circuit of the present invention.

Claims (1)

[Claims] 1. A shift register for inputting image data separated at predetermined intervals along a scanning line, a holding means for holding the output of the left register, and a holding means for shifting the shift register and holding the output thereof. a shift means for shifting to the means;
A first counter counts the number of shifts of the shift means and the count value is reset by an external signal, and a change in the state of the image data is detected by the output of the shift register and the output of the holding means. and the output of the detection means,
a circuit that blocks the shift when a state changes, and a circuit that counts the number of shifts in the shift register after the image data is input to the shift register, and when the shift of the number of image data is counted. A run-length counting circuit comprising: a second counter that generates an output signal.