JPS6122917B2 - - Google Patents

Description

[Detailed description of the invention] The present invention creates a ticking sound by an electronic circuit,
The present invention relates to an electronic time striking circuit that generates a sound, and its purpose is to provide an electronic time striking circuit that can generate a time striking sound simultaneously with the arrival of an hourly signal.

The present invention will be explained below with reference to Examples.

FIG. 1 is a diagram showing an embodiment of the electronic timing circuit of the present invention, in which numeral 1 is a crystal oscillation circuit using a crystal oscillator XL, which oscillates and outputs a fundamental frequency signal. 2
is a frequency dividing circuit consisting of 23 frequency dividing stages FF ₁ to _{FF 23} , and this frequency dividing circuit 2 inputs the output of frequency dividing stage FF ₃ to frequency dividing circuit 4, and also inputs the output from frequency dividing stage FF _{3 to frequency dividing circuit 4} . The output of the subsequent frequency dividing stage FF ₁₅ is input to the frequency dividing circuit 5. Furthermore, the output of the frequency dividing stage FF ₂₃ is output to the hand movement motor drive circuit 3 of the timepiece mechanism.
The frequency dividing circuit 4 further divides the output signal of the frequency dividing stage FF ₃ in six stages of frequency dividing stages FF ₂₄ to FF ₂₉ , and transmits the output of the final frequency dividing stage FF ₂₉ to the frequency dividing circuit 6 and the frequency dividing circuit 4. The signals are respectively input to the circuit 7, and in the frequency dividing circuit 6, the frequencies are divided by three frequency dividing stages FF ₃₀ to FF ₃₂ to obtain the first audio signal frequency ₁ . On the other hand, for frequency dividing circuit 7, 5
The second audio signal frequency ₂ is obtained by the frequency division stages FF ₃₃ to F ₃₇ of the stage. Both these signal frequencies
₁ and ₂ are input to the NOR circuit NOR ₁ and taken out as an audio clock signal. On the other hand, the frequency dividing circuit 5 has eight frequency dividing stages FF ₃₈ to FF ₄₅ , and these frequency dividing stages FF ₃₈ to _{FF 45} and the added NAND circuits NAND ₁ and NAND ₂ perform logic processing to generate a ticking sound. Generates a hammering period pulse signal to set the signal period. The motor drive circuit 3 is a NAND circuit
A pulse motor (not shown) is driven by a pulse signal processed by logic circuits such as NAND ₄ to NAND ₆ and outputted from inverters IN ₁ and IN ₂ to move the hands. 8 in the figure is a source switch (not shown)
This is a power-on detection section that detects when the power-on detection section 8 is turned on and outputs a pulse signal, and the pulse signal of this power-on detection section 8 determines the initial output of the flip-flop _F1 to be at the "1" level. Reference numeral 9 denotes an hourly signal generating circuit which operates when an hourly signal is input, and this hourly signal generating circuit 9 turns on the hourly signal switch _SW1 at the same time as the hourly signal is input, and outputs a signal. 10 is a time setting circuit, which is a switch
When SW ₂ is turned on, it outputs a signal for setting the output of the flip-flop F ₁ to the "0" level. 11 is a skip signal generating circuit that sets only one ticking sound, and 12 is a stop signal generating circuit that sets no ticking sound. These skip signal generating circuit 11 and stop signal generating circuit 12 The switch is rotary switch RS c
Consists of terminal and d terminal, rotary switch
A signal is generated when the switching contact r of the RS is switched to a predetermined terminal. The rotary switch RS has an a terminal and a b terminal separately, the a terminal constitutes a switch of the continuous striking sound generating circuit 13 for generating a continuous striking sound as desired, and the b terminal constitutes a switch for the time setting circuit 13. It is connected in series to the 10 switches _SW2 , and the respective operations can be performed by setting the a terminal to adjust the volume and the b terminal to set the time. Reference numeral 14 denotes an hour striking number setting circuit, which inputs the output signal (beating sound period pulse signal) from the frequency dividing circuit 5 through the NOR circuit NOR ₂ of the control circuit 15, counts it, and sets the striking sound for time setting. A predetermined number of periodic pulse signals or hammering periodic pulse signals for the hour are output to the attenuation circuit 16. 17 is a delay circuit for processing the percussion cycle pulse signal in order to delay only the last percussion sound by half a beat from the previous percussion interval; 18 is a delay circuit for amplifying the output signal of the attenuation circuit 16 and transmitting it to the speaker 19; This is an amplification section that generates a ticking sound. The control circuit 15 performs a NOR gate on the output of the skip signal generating circuit 11, the tapping sound period pulse signal, and the _Q1 output of the shift register 13a of the continuous hitting sound generating circuit 13 using a NOR circuit _NOR2 . ₁ output is at the "1" level, or if the output of the skip signal generating circuit 11 is at the "1" level, the striking period pulse signal is not input to the hour striking number setting circuit 14. 23
is a reset circuit for the frequency divider circuit 5, and is composed of a shift register 20, etc., and a flip-flop circuit.
At the same time that the output of _F1 becomes "L" level, the NOR circuit _NOR3 outputs a signal for resetting the frequency dividing stages _FF38 to _FF45 of the frequency dividing circuit 5. Next, to further explain the operation of the reset circuit 23 using the time chart shown in FIG. 2, the clock pulse T as shown in FIG. When the hour signal switch SW ₁ is activated by the hour signal from the clock mechanism and turned on, and a signal as shown in Figure 2 b is input, one signal as shown in Figure 2 c is input from the NOR circuit NOR ₈ . When the output is to be output, the output of the flip-flop F1, which was at the " ₁ " level, is set to the "0" level (FIG. 2d). Due to this inversion of the output of the flip-flop _F1 , the input signal of the shift register 20 constituting the reset circuit 23 is inverted by the inverter _IN3 to the "1" level as shown in FIG. 2e. As a result, _{the signal} shown in _FIG . Figures 2g to 1 show charts of the outputs of the frequency dividing stages FF ₄₀ to FF _45. At the same time as the output of the frequency dividing stage FF ₄₀ rises, the output is transmitted through the NAND circuit NAND ₁ and the NOR circuit NOR ₄ . The first hitting sound period pulse signal is output as shown in Fig. 2m. This first hitting sound period pulse signal is input to the attenuation circuit 16 and transferred to the transfer gate.
TG ₂ and TG ₃ are turned on and the audio clock signal as shown in FIG. 2 n is inputted to the attenuation circuit 16 as shown in FIG. It forces you. In other words, the reset circuit 23 can generate the hour tone almost simultaneously with the arrival of the hourly signal.

Next, the operation of the electronic timing circuit of the present invention will be explained in detail with reference to the time charts of FIGS. 3 and 4.

Now, when the power switch (not shown) is turned on, a pulse signal is generated from the power-on detection section 8 as shown in FIG. 3a, and the output state of the flip-flop _F1 is changed as shown in FIG. 3b. Set to 1” level. Next, when the rotary switch RS is switched to the b terminal and the switch SW ₂ of the time setting circuit 10 is turned on, the pulse signal α shown in _{FIG .} When reversed to “0” level,
Input data to shift register 20 and run NOR circuit
A pulse signal is outputted from NOR ₃ as shown _{in FIG} . Then, an instant after the Q ₄₀ output of the frequency dividing stage FF ₄₀ reaches the "1" level, a hammering periodic pulse signal as a frequency divided output is outputted from the NAND circuit NAND ₁ as shown in Fig. 3 f, and is further passed through the delay circuit. 17 Noah circuits
The signal is output to the attenuation circuit 16 via NOR ₄ and NOR ₅ , turns on and off the transfer gates TG ₂ and TG ₃ , and causes the speaker 19 of the amplification section 18 to sound. At this time, the audio clock signal from the NOR circuit NOR ₁ is modulated by turning on and off the transfer gates TG ₂ and TG ₃ using the above-mentioned striking period pulse signal, and becomes a striking signal having a predetermined tone. Incidentally, the pulse width of the percussion periodic pulse signal is determined by the frequency dividing stages _FF38 to _FF45 . Furthermore, the inverter of the frequency divider circuit 4
IN ₄ , IN ₅ and inverter IN ₆ of frequency divider circuit 7,
IN ₇ and inverters IN ₈ and IN ₉ of frequency dividing circuit 5 increase the reset width of each frequency dividing stage of frequency dividing circuits 4, 5, and 7 to ensure counter operation. Now, the striking periodic pulse signal output from the NAND circuit NAND ₁ is simultaneously input to the hour striking number setting circuit 14 via the NOR circuits NOR ₄ and NOR ₅ . That is, the counter _C1 is reset at the time when the above-mentioned switch _SW2 is turned on, and the hitting sound period pulse signal is inputted as shown in FIG. 3i. At this time, the pulse signal α of the NOR circuit NOR ₆ <Fig. 3 c> is applied to the flip-flop as shown in Fig. 3 h.
In order to set the output of _F2 to the "0" level, the hammering period pulse signal is controlled not to be input to the preset counter _C2 , and at the same time, the counter _C1
The complement of the data is set in parallel to each bit of preset counter _C2 . When the switch SW ₂ is turned off after the time setting is completed, one pulse signal β is outputted from the NOR circuit NOR ₇ as shown in FIG. 3d, and the output of each bit of the counter C ₁ is advanced by one. This is the next time the hour signal comes in and the counter C ₁ is used to sound the next time number after the time that was set.
For example, when the time is set at 4 o'clock, five pulse signals are input to the counter _C1 , and at the same time, the flip-flop _F1 is inverted and its output is set to the "1" level. Therefore, although the output of the NAND circuit NAND ₁ exists, the output of the NOR circuit NOR ₄ , that is, the output of the percussion periodic pulse signal to each part is stopped. 3j to m show the _Q1 output, _Q2 output, _Q4 output, and _Q8 output of the counter _C1 . Now, in this state, the hour signal is input to the hour signal generation circuit 9.
A pulse signal is output from the NOR circuit NOR ₈ as shown in FIG. 4a, and the flip-flop _F1 is inverted so that its output is set to the "0" level, and a periodic pulse signal is output in the same manner as in the above-mentioned time adjustment. At the same time, the flip-flop _F2 is inverted and the output is set to the "1" level, and the hammering period pulse signal is not input to the counter _C1 , but is input to the preset counter _C2 as shown in Figure 4b. The hour stroke number setting circuit 14 is controlled as follows. Now, as mentioned above, when "time setting" is performed, the complement of the data of counter _C1 or each bit of preset counter _C2 is set in parallel.
In this state, there are five pieces of data, ie, [0101], in the counter _C1 , and therefore, in the preset counter _C2 , the complement number [1010] is set in parallel to each bit. Therefore, the moment the flip-flop _F2 outputs a "1" level, the input C of the preset counter _C2 becomes a "1" level, and one pulse is sent to the _Q1 output of the preset counter _C2 to start counting. do. Therefore, since one count is made before the hitting sound period pulse signal is input to the preset counter _C2 , the count contents of [1010] of each Q ₈ , Q ₄ , Q ₂ , and Q ₁ become [1011]. After that, each time one hammering period pulse signal is input, the count changes as [1100], [1101], [1110], [1111], [0000], and the preset counter _C2 is subtracted. Functions as a circuit. FIGS. 4c to 4f show the outputs of each bit Q ₁ , Q ₂ , Q ₄ , Q ₈ of the preset counter C ₂ . That is, subtracting 5 from the initially set number (for example, 5's complement) becomes 0. For example, when striking 5 o'clock on the hour, if you want to distinguish the five hour sounds, that is, the "final sound" from the other sounds, you would like to distinguish the 5 o'clock sounds, that is, the "final sound" from the other sounds. By using the fifth bit output [1111] to detect the fifth note, it is possible to change the striking interval and decay time. This [1111] is detected by the NAND circuit NAND ₃ , and when each bit output of the preset counter _C2 becomes zero at [1111], it produces an output to the delay circuit 17 as shown in Fig. 4g, nand circuit
The hammering periodic pulse signal output from NAND ₁ via NOR circuit NOR ₄ is stopped. On the other hand, the NAND circuit
NAND ₂ uses the above NAND circuit in order to delay the "end note" by half a beat compared to the previous note interval.
At the same time as the NAND ₁ outputs the striking period pulse signal, a similar striking period pulse signal is outputted with a delay of half a beat as shown in FIG _. When an output is generated, the output of the NAND circuit NAND ₂ is transferred to the flip-flop through the NOR circuit NOR ₉ as shown in Figure 4h.
2-bit counter _C3 consisting of FF ₄₆ FF ₄₇
This will be entered into. This counter _C3 switches the percussion period pulse signal from the NAND circuit NAND ₁ to the NAND circuit NAND ₂ , and at the same time, if this percussion period pulse signal is used for the percussion sound, the percussion sound will be output half a beat earlier. The tapping period pulse signal from this NAND circuit NAND ₂ is counted as shown in Figure 4 i and j, and the 2nd bit is output, that is, a signal delayed by 1 bit with respect to the preceding tapping period pulse signal. The output of this striking period pulse signal is inputted to the preset counter C ₂ of the hour striking number setting circuit 14 via the NOR circuit NOR ₅ and the NOR circuit NOR ₂ of the control circuit 15. Let the bit output be from [1111] to [0000]. Therefore, a signal is generated from the OR circuit _OR1 and input to the register 21. Then, by the output of the register 21,
An output is generated in _the NOR circuit _NOR10 as shown in _FIG . By turning off the transfer gate _TG1 , the resistor _Rg is disconnected from the attenuation loop. That is, the attenuation circuit 16 is a capacitor CO
The attenuation loop is made up of a parallel circuit of resistor R _h and resistor R _g , but when resistor R _g is disconnected, the attenuation time constant becomes τ = CO・R _h and increases. , the decay time becomes longer. Therefore, the "end of beat sound" detected by each bit output [1111] that is the counter content of preset counter _C2 has a longer reverberation than the previous time beat sound. At this time, the Q of register 21 is output at the same time as the hitting sound is output.
_{The g3} output outputs a hitting sound stop signal, sets the output state of the flip-flop F1 to " ₁ " level, and sends the hitting sound period pulse signals from the NAND circuits NAND ₁ and NAND ₂ to the NOR circuits NOR ₄ and NOR ₉ . By closing, output to each part is stopped. At the same time, the above Q _g3 output is outputted from the counter _C1 , and the contents of the counter are set to the number of strokes at the next hour. At this time, flip-flop _F2 is inverted and set to "O" level, and the contents of counter _C1 are transferred to the preset counter.
Open gate 22 to set parallel to _C2 . In this way, it stands by for the next hourly signal. Fig. 4 k shows the output of the OR circuit OR ₁ , and l, m, n in the same figure show each Q of the register 21.
_g1 , Q _g2 , Q _g3 outputs are shown, and o in the same figure shows the output of the NOR circuit NOR ₁₀ , and the time scales of these m to o are expanded. Further, FIG. 4p shows the striking periodic pulse signal train when setting the time and when the hour is on the hour. In addition, SW _B in the figure is a switch for canceling the reset. Normally, this switch SW _B is set to output a "1" level signal, and this switch SW _B is set to output a "0" level signal. When the frequency dividing stages _FF19 to _FF22 are reset, the output of the motor drive circuit 3 is stopped, and the movement of the hands can be stopped.

The present invention is constructed as described above, and is further provided with a reset means for resetting and activating the frequency division stage for setting the generation interval of the hourly sound signal when the hourly signal coming from the clock mechanism is input. This has the excellent effect of being able to accurately emit a striking sound at zero seconds on the hour when the clock mechanism section is on the hour, thereby providing an accurate time signal.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of one embodiment of the present invention, Fig. 2 is a time chart of various parts for explaining the operation of the reset circuit used in the above, Fig. 3 and Fig. 4 are for explaining the overall operation of the same. This is a time chart of each part, 1 is a crystal oscillation circuit, 5 is a frequency dividing circuit,
NAND ₁ and NAND ₂ are NAND circuits, FF ₃₃ to _{FF 45} are frequency dividing stages, and 23 is a reset circuit.

Claims (1)

[Claims] 1. A crystal oscillation circuit, a frequency division means for dividing the oscillation frequency of this crystal oscillation circuit, and a plurality of units for inputting the output from a predetermined frequency division stage of this frequency division means and setting the interval of the striking signal when the frequency is further divided. a frequency dividing stage and a gate means for outputting a ticking sound signal to the generating means when the frequency division outputs from the first and subsequent stages of the frequency dividing stage that set the intervals of these ticking sound signals match; The above-mentioned sounding means generates a striking sound based on the striking sound signal obtained by the output of the means, and the striking logic means controls the number of striking sounds by counting the striking sound signal. An electronic hour striking circuit characterized in that the electronic hour striking circuit is equipped with a reset means for resetting and activating a frequency dividing stage for setting the interval of the hour striking signal when an hourly signal coming from a clock mechanism section is input. circuit.