JPS612346A - Manufacture of multilayer interconnection - Google Patents

Abstract

PURPOSE:To enable to form the contact site of one side of the lower wiring layers in a self-matching way and to prevent connection failure and connection resistance from increasing by a method wherein the contact site is covered with a masking material, the other site of the other side is exposed and an etching is performed on the other side of the lower wiring layers. CONSTITUTION:Firstly, an insulating film 2 is formed on a substrate 1 whereon a semiconductor element is constituted. Then, lower wiring layers 8, each consisting of metal films 4, 6 and 5 in a three-layer structure, are formed, and then, a first photo resist film 9, an SOG film 10 and a second photo resist film 11 are formed. After that, such treatments as exposure, developing and etching are performed. Whereby the lower wiring layers 8 are brought in a condition that the contact site 12 only of one side of the wiring layers 8 is covered and the other site of the other side is exposed. Then, an etching is performed on the exposed top film 4 of the lower wiring layer 8 in a self-matching manner. After that, the films 9 and 10 are removed and an insulating film 13 is formed. An etching is performed on the film 13 and after the contact site 12 is made to be exposed, an upper wiring layer 14 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to electrode wiring technology, and in particular to a technology that is effective for use in manufacturing multilayer wiring with high integration and improved reliability.

[Background technology]

Generally, in a semiconductor device with a multilayer wiring structure, a through hole is formed in an insulating film formed between upper and lower wirings, and a part of the upper wiring is extended into the opening of this through hole. The wiring and the lower wiring are electrically connected. The through holes are formed by forming a mask on the insulating film using photoresist technology and partially etching the insulating film using this mask. However, the inventors have found that the following problems occur as the miniaturization progresses.

(1) If an anisotropic dry etching method, which is advantageous in terms of miniaturization, is used for etching through-holes, a steep slope will be formed at the opening of the through-hole, and the upper wiring material at the opening will be It becomes difficult to attach the wire and the wire breaks.
This causes a decrease in reliability due to increased resistance, etc. This type of hole also has an aspect ratio (ratio of hole depth to low area).
As this increases, the angle of incidence of Ar+ ions for sputter etching (removal of insulators that impede conduction) entering this hole becomes smaller, reducing the sputter etching efficiency and preventing contact between conductive parts. It becomes difficult to reduce or stabilize the resistance.

(2) The photoresist technology used to form through holes requires a mask, but there is a limit to the improvement in alignment accuracy of this mask, and some alignment errors are unavoidable. For this reason, deep and steep grooves (flavas) are formed in the lower part of the formed through hole at the side of the lower wiring at the mask alignment misalignment between the through hole and the lower wiring.
Not only is it extremely difficult to attach the upper wiring material to this portion, but reliability is also lowered, such as deterioration of breakdown voltage between adjacent wirings.

A document that describes dry etching technology is Electronic Materials 1981 special issue, Kogyo Kenkyukai, published in 1972.
Published November 10, 2015, pages 131-136. Further, as a document describing the photoresist technology, there is a separate issue of Electronic Materials 1983, published by Kogyo Kenkyukai, November 15, 1980, pages 92 to 96.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer interconnection manufacturing technique that can achieve high integration, improve the reliability of connections between upper and lower interconnections, and facilitate the formation of contact structures.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the lower wiring is etched to reduce the film thickness while covering only the contact area of the lower wiring formed in multiple layers, and an insulating film is formed on the upper surface of the parenthesis and then etched back to expose only the contact area. By forming the upper wiring on top of that, there is no need to form through-holes, and a contact structure can be constructed in a self-aligned manner.This allows for highly reliable wiring contacts, and its miniaturization allows for high integration. can be achieved.

〔Example〕

FIGS. 1A to 1J show an example in which the present invention is applied to the manufacture of a semiconductor device having a two-layer wiring structure including lower wiring and upper wiring in the order of steps.

First, as shown in FIG. 2A, an impurity diffusion layer is formed on a semiconductor substrate 1 made of single crystal silicon to form a semiconductor element (for example, a bipolar transistor, an MO8 type transistor, etc., not shown), and then A thin insulating film 2 of silicon dioxide is then formed.

Then, on this insulating film 2, a metal film 3 for forming the lower wiring 8 is formed by, for example, a vapor deposition method. In this case, the metal film 3 is formed in three layers, including relatively thick upper and lower films 4.5 and a thin film 6 in the middle. Upper and lower membranes 4.
For material 5, aluminum alloy with good conductivity is used.
For the intermediate film 6, tantalum, tungsten, molybdenum, or the like, which has a slower etching rate than aluminum alloy, is used as an etching stopper film. Further, the thickness of each of the upper, middle, and lower films 4.6.5 is, for example, 1.5 μm.

Then, the metal film 3 is set to 0.2 μm and 1.0 μm.
A mask member 7 for lower wiring patterning, for example, a photoresist film, is patterned on the mask member 7.
The upper, middle, and lower films 4.6.5 are sequentially dry-etched using a dry etching method. As a result, the lower wiring 8 shown in FIG. 3B is formed.

Next, as shown in FIG. 2C, a first photoresist film 9 is coated to a thickness greater than the surface height of the upper film 4 of the lower line 8, and a first photoresist film 9 is formed on top of the first photoresist film 9 as an intermediate film. 0, and then a second photoresist film 11 is formed thereon. Then, the second photoresist film 11 is exposed and developed so that the second photoresist film 11 remains only at the contact portion 12 of the lower wiring 8 (a portion to be connected to the upper wiring 14 described later). . continue,
Next, the SoG film 10 is etched using the remaining second photoresist film 11 as a mask (FIG. D). Next, using the SOG as a mask, the first photoresist film 9 is
For example, as shown in the same figure (E), the first photoresist film 9 and the SOG film 1 are removed by oxygen plasma asher, and only the contact area 12 of the lower wiring 8 is covered, and the other parts are exposed. state.

In this case, when aligning the mask of the second photoresist film 11, an alignment error within the range of ΩS shown in the figure can be tolerated. Furthermore, it is important to leave the first photoresist film 9 on the entire surface, which will be described later. The planar state of FIG. 2(E) is shown in FIG.

Next, as shown in FIG. 1(F), the first photoresist film 9
, and the exposed upper film 4 of the lower wiring 8 on the SOG film 1 is etched in a self-aligned manner by dry etching. As a result, the media 6 with etching selectivity
acts as a stopper, and only the upper film 4 is etched. Needless to say, the contact region 12 is not etched at this time. Thereafter, the first photoresist film 9 and the SOG film 1 are removed to obtain the structure shown in FIG. 3(G).

Then, as shown in FIG. 6H, an insulating film 13 of silicon dioxide is formed to a thickness of, for example, 3.0 μm, which covers the entire lower interconnection 8, using a planar bias sputtering technique. It is already known that this insulating film 13 is formed with a flat top surface, and therefore this insulating film 1
By proceeding with etching 3 from the top surface, only the contact portion 12 of the lower wiring 8 is exposed.

Then, in this state, if the etching is stopped and the structure shown in the figure (D) is obtained, and then the upper wiring 14 is formed on the insulating film 13 by the usual method, each of the lower and upper wirings in the contact 1 to region 12 is formed. A connection of 14.8 is obtained, completing the multilayer wiring shown in FIG.

Therefore, according to this manufacturing method, there is no need to form the contact 1-hole by etching, and various problems associated with the steep shape of the hole can be prevented. on the other hand,
In the etching of the lower wiring when forming the contact portion 12 in the lower wiring 8, self-alignment is achieved by the action of the intermediate film 6 as a stopper provided on the lower wiring 8 and the masking action of the first photoresist 9 and 5OGIO. This can be done without causing problems due to mask alignment errors. Furthermore, since the contact portion 12 of the lower wiring 8 is directly used for connection with the upper wiring 14,
Contact resistance can also be reduced, and stability and reliability can be improved. Further, since the 9 is left on the first photoresist 1 when etching the lower wiring, no etching damage is caused to the semiconductor substrate 1. Furthermore, since the contact portion 12 can be formed extremely finely, it is possible to miniaturize the device.
Effective for high integration.

〔effect〕

(1) Since the contact part of the lower wiring is covered with a mask material such as a photoresist film and the other parts are exposed before etching of the lower wiring, the contact 1 part can be formed in a self-aligned manner. This makes it possible to reliably prevent connection failures and increases in connection resistance due to mask alignment errors, etc., thereby improving the reliability of wiring.

(2) Since a part of the lower wiring is formed by self-aligned etching as the contact 1~ region, the contact portion can be miniaturized compared to the method using a mask.
This makes it possible to achieve high integration.

(3) Since the lower wiring has a multilayer (three-layer) structure and an intermediate film is formed as an etching stopper in the middle, it is possible to extremely easily control etching when etching the lower wiring other than the contact area.

(4) Since the mask member is left on the semiconductor substrate when etching the lower wiring, the semiconductor substrate can be protected from etching damage.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, although the lower wiring is formed in three layers, it may be formed in two or four or more layers depending on the relationship with the etching selectivity. Furthermore, other organic resins or the like can be used for the first and second photoresist films as masks. Of course, the material of the insulating film and its manufacturing method can also be changed as appropriate.

[Application field]

In the above explanation, the invention made by the present inventor was mainly applied to the multilayer interconnection of monolithic semiconductor devices, which is the background field of application, but the invention is not limited thereto. It can be applied to multilayer wiring of semiconductor devices. Moreover, it can also be applied to a wiring structure of three or more layers.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1J are manufacturing process diagrams of an embodiment of the present invention, and FIG. 2 is a plan view of FIG. 1E. 1... Semiconductor substrate, 2... Insulating film, 3... Metal film,
4... Upper film, 5... Lower film, 6... Middle film, 8... Lower wiring, 9... First photoresist film, 10... S
OG film, 11... second photoresist film, 12... contact region, 13... insulating film, 14... upper wiring. Figure 1 Figure 1 (D Figure 1 Figure 1 Figure 2 // 〆Z

Claims (1)

[Claims] 1. A step of forming a multilayer lower wiring having layers with different etching ratios on a substrate, and a step of forming a mask member that covers only the contact portion of the lower wiring and exposes other portions. a step of etching the exposed lower wiring down to the layer having the different etching ratio; a step of forming an insulating film on the lower wiring; and a step of etching back the insulating film to expose only the contact portion. A method for manufacturing a multilayer interconnection comprising the step of forming an upper interconnection layer to be connected to the contact portion. 2. The multilayer wiring according to claim 1, in which the lower wiring is formed in a three-layer structure of upper and lower aluminum alloy films and an intermediate film of tungsten or the like whose etching rate is slower than that of the Al alloy. manufacturing method. 3. The method of manufacturing a multilayer wiring according to claim 1 or 2, wherein the mask member is formed of at least two layers of photoresist, and the upper photoresist is pattern-etched. 4. The method of manufacturing a multilayer wiring according to claim 1 or 3, wherein the insulating film is formed to have a flat upper surface by planar bias sputtering technology.