JPS61237509A - Schmitt trigger circuit - Google Patents

Schmitt trigger circuit

Info

Publication number
JPS61237509A
JPS61237509A JP7780785A JP7780785A JPS61237509A JP S61237509 A JPS61237509 A JP S61237509A JP 7780785 A JP7780785 A JP 7780785A JP 7780785 A JP7780785 A JP 7780785A JP S61237509 A JPS61237509 A JP S61237509A
Authority
JP
Japan
Prior art keywords
channel
moses
transistors
parallel
mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7780785A
Other languages
Japanese (ja)
Inventor
Hideo Nakada
英夫 中田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7780785A priority Critical patent/JPS61237509A/en
Publication of JPS61237509A publication Critical patent/JPS61237509A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To vary digitally a threshold value by connecting >=2 sets of same channel control MOSes in parallel with each MOS of an inverter comprising series connection of P and N-channel MOSFETs (MOS). CONSTITUTION:Plural P-channel MOSes 8 are connected in parallel with a P-channel MOS 7 and N-channel MOSes 12 are connected similarly in parallel with N-channel MOS 11. An output signal at an output terminal 3 is given to a control input terminal 5 of a gate control circuit 6 to be inputted to a MOS selected out of P and N-channel MOSes 8 and 12 so as to control its conduction. The MOSes not selected are always in cut-off state. The number of transistors conducted or cut off in the MOSes 8, 12 connected in parallel is controlled depending on the number of high level signals inputted to the control input terminal 5. The threshold voltage of this circuit is controlled by the number.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、シ二ミット・トリガ回路に関する。[Detailed description of the invention] [Industrial application field] FIELD OF THE INVENTION The present invention relates to a sinimit trigger circuit.

〔従来の技術〕[Conventional technology]

従来の相−1llIi!!!1MO8トランジスタを用
い几シュミット・トリガ回路は、2つのPチャンネルf
iM08を界効果トランジスタと2つのNチャンネル型
M0811界効果トランジスタ全電源間に直列に接続し
、各MO811界効果トランジスタのゲート電極に入力
信号を共通に加え、直列接続MO8電界効果トランジス
タの中間接続点から出力信号を得るとともに、この出力
信号によって2つのPチャンネル型M08@界効果トラ
ンジスタの一万ト2つのNチャンネル型MUM1!界効
果トランジスタの−1とにそれぞれ並列接続されfcM
O8II界効果トランジスタ七オンもしくはオフせしめ
て全体の回路の入力信号に対する閾値電圧’kf更せし
めていた。
Conventional phase-1llIi! ! ! A Schmitt trigger circuit using 1 MO8 transistor has two P-channel f
iM08 is connected in series between a field effect transistor and two N-channel type M0811 field effect transistors, and an input signal is commonly applied to the gate electrode of each MO811 field effect transistor, and an intermediate connection point of the series connected MO8 field effect transistors is connected in series. At the same time, this output signal is used to generate two P-channel type M08@ field effect transistors and two N-channel type MUM1! -1 of the field effect transistor, respectively, and fcM
The O8II field effect transistor was turned on or off to increase the threshold voltage 'kf of the entire circuit for the input signal.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

かかる従来のシュミット・トリガ回路は、トリガー室圧
、すなわち上下のしきい値電圧は回路的に定まってしま
い、集積回路化した場合、トリガー電圧t−変更するこ
とができなかった。この几め。
In such a conventional Schmitt trigger circuit, the trigger chamber pressure, that is, the upper and lower threshold voltages are determined by the circuit, and when integrated into an integrated circuit, the trigger voltage t cannot be changed. This method.

シュミット・トリガ回路を用い友システムにこのシュミ
ット・トリガ回路のトリガー電圧が適合しない場合には
シュミット回路そのものt1再設計しなければならない
という欠点があ−)几。
If the trigger voltage of the Schmitt trigger circuit is not suitable for the system using the Schmitt trigger circuit, the Schmitt circuit itself has to be redesigned (t1).

〔問題A?解決するための手段〕[Question A? Means to solve]

本発明のシュミット・トリガー回路は、正および負の!
#間に各々複数個のPチャンネルおよびNチャンネルM
OSトランジスタのソースが直列に接続され、これら直
列接RされたM08トランジスタの各ゲートは共通に入
力端子に接続され、Pチャンネルお工びヘチャンネルの
トランジスタの少なくともおのおの1つに並列に2個以
上の同一チャンネル形の制御用M(Jlトランジスタが
接続され、直列接続の中間接続点から得られる出力信号
でもりて制御用MO8トランジスタの4通を制御してい
る。
The Schmitt trigger circuit of the present invention has positive and negative !
# Each of a plurality of P channels and N channels M between
The sources of the OS transistors are connected in series, the gates of the M08 transistors connected in series are commonly connected to the input terminal, and two or more transistors are connected in parallel to at least one of the transistors in the P-channel channel. The control M(Jl) transistors of the same channel type are connected, and the four control MO8 transistors are controlled by the output signal obtained from the intermediate connection point of the series connection.

〔実施例〕〔Example〕

次に、画面全参照して、本発明?説明する。 Next, see the entire screen and see the invention? explain.

第1図は本発明の一実施例であり、1に、シュミット・
トリガー回路の入力端子、3は出力端子である。正の’
FJ! #、 m子2と負のtgp、端子4との間に2
つのPチャンネルMO8)ランジスタフ、9と2つのN
チャンネルトランジスタ10.11が直列に接続されて
いる。PチャンネルMOSトランジスタ7に並列に複数
のPチャンネルMOSトランジスタが接続されており、
同様にNチャンネルMO8)ランジスタ11に並列に複
数のNチャンネルMO8)ランジスタ12が接続されて
いる。
FIG. 1 shows an embodiment of the present invention.
The input terminal 3 of the trigger circuit is an output terminal. Positive'
FJ! #, 2 between m child 2 and negative tgp, terminal 4
one P channel MO8) Langistav, 9 and two N
Channel transistors 10.11 are connected in series. A plurality of P-channel MOS transistors are connected in parallel to the P-channel MOS transistor 7,
Similarly, a plurality of N-channel MO8) transistors 12 are connected in parallel to the N-channel MO8) transistor 11.

直列接続されたトランジスタ7.9,10.]1の中間
接続点からの出力はインバータ13全介して出力端子3
に得られ、この出力端子3の出力信号はゲート制御回路
6の制御入力端子5によってPチャンネルMOSトラン
ジスタ8とへチャンネルMOSトランジスタ12の選択
されたものに入力されてその導通を制御している。選択
されないものは常に遮断状態となっている。
Series connected transistors 7.9, 10. ]The output from the intermediate connection point 1 is sent to the output terminal 3 through the inverter 13.
The output signal from the output terminal 3 is inputted to a selected one of the P-channel MOS transistor 8 and the H-channel MOS transistor 12 by the control input terminal 5 of the gate control circuit 6 to control the conduction thereof. Items that are not selected are always in a blocked state.

本実施例では、制御入力端子5に入力される高レベルの
信号の数に工9並列に接続されたMO8トランジスタ8
.および12の導通もしくは遮断するトランジスタの数
音制御することが可能となる。この数により、シュミッ
ト・トリガー回路のしきい値電圧が制御でき、シシミッ
ト電圧幅を制御できる。具体的lCは出力信号により導
通もしくは遮断となるトランジスタの数を増やすことに
よりクエミット電圧暢全広げることができる。
In this embodiment, MO8 transistors 8 are connected in parallel to the number of high-level signals input to the control input terminal 5.
.. And it becomes possible to control the number of transistors to conduct or cut off the 12 transistors. By this number, the threshold voltage of the Schmitt trigger circuit can be controlled, and the Schmitt voltage width can be controlled. Specifically, the quamit voltage range of IC can be widened by increasing the number of transistors that are turned on or off depending on the output signal.

〔発明の効果〕〔Effect of the invention〕

以上説明し友工うに、本発明によれば任意にシ瓢ミツト
・トリガ電圧全ディジタル的に可変できるシュミット・
トリガ回路を得ることができる。
As explained above, according to the present invention, the Schmitt trigger voltage can be arbitrarily varied completely digitally.
Trigger circuit can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例金示す回路図である。 l・・・入力端子、2・・・電源端子、3・・・出力端
子、4・・・負電源端子、5・・・制御信号入力端子、
6・・・ゲート制御回路、7,8.9・・・Pチャンネ
ルMOSトランジスタ、10,11.12・・・Nチャ
ンネルMOSトランジスタ、13・・・インバータ回路
代理人 弁矧+  内 泊   普・/′;:’t+ 
゛・、葛1図
FIG. 1 is a circuit diagram showing one embodiment of the present invention. l...input terminal, 2...power supply terminal, 3...output terminal, 4...negative power supply terminal, 5...control signal input terminal,
6...Gate control circuit, 7,8.9...P channel MOS transistor, 10,11.12...N channel MOS transistor, 13...Inverter circuit agent ′;:'t+
゛・, Kudzu 1

Claims (1)

【特許請求の範囲】[Claims] それぞれ複数のPチャンネルおよびNチャンネル電界効
果トランジスタを電源端子間に直列接続し、各電界効果
トランジスタのゲートに共通に入力信号を加え、これら
直列接続された電界効果トランジスタの中間接続点から
得られる信号から出力信号を得、前記Pチャンネルおよ
びNチャンネル電界効果トランジスタの各々所定のもの
に並列にそれぞれ複数の制御用トランジスタを有してお
り、前記中間接続点から得られる信号を前記複数の制御
用トランジスタの選択されたものの入力電極に加えたこ
とを特徴とするシュミット・トリガー回路。
A plurality of P-channel and N-channel field-effect transistors are each connected in series between power supply terminals, an input signal is commonly applied to the gate of each field-effect transistor, and a signal obtained from the intermediate connection point of these series-connected field-effect transistors. A plurality of control transistors are provided in parallel to predetermined ones of each of the P-channel and N-channel field effect transistors, and a signal obtained from the intermediate connection point is output from the plurality of control transistors. A Schmitt trigger circuit characterized by the addition of selected ones of the input electrodes to the input electrodes.
JP7780785A 1985-04-12 1985-04-12 Schmitt trigger circuit Pending JPS61237509A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7780785A JPS61237509A (en) 1985-04-12 1985-04-12 Schmitt trigger circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7780785A JPS61237509A (en) 1985-04-12 1985-04-12 Schmitt trigger circuit

Publications (1)

Publication Number Publication Date
JPS61237509A true JPS61237509A (en) 1986-10-22

Family

ID=13644286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7780785A Pending JPS61237509A (en) 1985-04-12 1985-04-12 Schmitt trigger circuit

Country Status (1)

Country Link
JP (1) JPS61237509A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0188524U (en) * 1987-12-04 1989-06-12
JPH0191333U (en) * 1987-12-07 1989-06-15
US5874844A (en) * 1997-03-20 1999-02-23 Lg Semicon Co., Ltd. Schmitt trigger circuit with an adjustable trigger voltage
KR100401505B1 (en) * 2001-05-10 2003-10-17 주식회사 하이닉스반도체 Programmable schmitt trigger circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0188524U (en) * 1987-12-04 1989-06-12
JPH0191333U (en) * 1987-12-07 1989-06-15
US5874844A (en) * 1997-03-20 1999-02-23 Lg Semicon Co., Ltd. Schmitt trigger circuit with an adjustable trigger voltage
KR100401505B1 (en) * 2001-05-10 2003-10-17 주식회사 하이닉스반도체 Programmable schmitt trigger circuit

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