JPS6124829B2 - - Google Patents
Info
- Publication number
- JPS6124829B2 JPS6124829B2 JP51074519A JP7451976A JPS6124829B2 JP S6124829 B2 JPS6124829 B2 JP S6124829B2 JP 51074519 A JP51074519 A JP 51074519A JP 7451976 A JP7451976 A JP 7451976A JP S6124829 B2 JPS6124829 B2 JP S6124829B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- layer
- substrate
- impurity
- capacitance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000012535 impurity Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000011159 matrix material Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 27
- 230000015654 memory Effects 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 6
- 238000003860 storage Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
本発明はMOS−FETを用いた半導体装置、特
に半導体メモリの性能改善に係わる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the performance of semiconductor devices using MOS-FETs, particularly semiconductor memories.
最近、第１図Ａに示すような、MOS−FET、
Ｑおよび情報電荷を記憶する容量Csからなるメ
モリ回路が注目を集めている。同図で１２はそれ
ぞれデータ線、ワード線である。 Recently, MOS-FET, as shown in Figure 1A,
A memory circuit consisting of Q and a capacitor Cs for storing information charges is attracting attention. In the figure, numerals 12 are data lines and word lines, respectively.
このようなメモリ回路では、Csとデータ線に
寄生容量として生じるＣDの容量比で動作の安定
度が支配され、Cs／ＣDが大なるほど望ましい。 In such a memory circuit, the stability of operation is determined by the capacitance ratio between Cs and C D generated as a parasitic capacitance in the data line, and the larger Cs/C D is, the more desirable it is.
第１図Ｂ，Ｃはｎチヤンネル形シリコンゲート
MOS−FETを用いた従来技術によるメモリ回路
を説明するもので、それぞれ平面図および断面構
造を示しており、同図Ｂの太線枠２０がメモリ回
路１ビツトの領域を示している。 Figure 1 B and C are n-channel silicon gates.
This is to explain a memory circuit according to the prior art using MOS-FET, and shows a plan view and a cross-sectional structure, respectively, and the thick line frame 20 in FIG.
３はＰ形不純物のシリコン基板である。４は、
素子間分離用のパターン（フイールドパターン）
であり、その外側は１μｍ程度の厚いシリコン酸
化膜５でおおわれている。６はMOS−FETのゲ
ート絶縁膜となる1000Å程度の薄いシリコン酸化
膜であり、２ａ〜２ｃ，２ｘ〜２ｙはゲート電極
となる多結晶シリコンである。７はMOS−FET
のドレイン、ソース電極となるN+拡散層であ
る。１は配線導体となるAl層であり、ここでは
データ線として用いている。８は、１と多結晶シ
リコンおよび拡散層の層間絶縁膜となるリンガラ
ス（PSG）であり、９は相互の接続を行なうため
の、層間連絡孔である。 3 is a silicon substrate containing P-type impurities. 4 is
Pattern for isolation between elements (field pattern)
The outside thereof is covered with a silicon oxide film 5 having a thickness of about 1 μm. 6 is a thin silicon oxide film of about 1000 Å which becomes a gate insulating film of the MOS-FET, and 2a to 2c and 2x to 2y are polycrystalline silicon films which become gate electrodes. 7 is MOS-FET
This is an N + diffusion layer that becomes the drain and source electrodes. Reference numeral 1 denotes an Al layer serving as a wiring conductor, and is used here as a data line. 8 is phosphor glass (PSG) serving as an interlayer insulating film between 1 and the polycrystalline silicon and the diffusion layer, and 9 is an interlayer communication hole for mutual connection.
このような構造において、メモリ回路の記憶容
量Csa〜Cscは第１図Ｂに斜線で示したように、
２ｘ〜２ｙと４が重なつた部分に形成される。す
なわち、２ｘ，２ｙの電極には電源電圧Ｖpが印
加されるが、Ｖpの値はMOS−FETのしきい電圧
ＶTよりも、高く設定してあるため２ｘ，２ｙの
直下には反転層１０を生じ、２ｘ，２ｙおよび１
０を電極、６を誘電体とする容量をCsa〜Cscの
容量として用いるわけである。 In such a structure, the storage capacity Csa to Csc of the memory circuit is as indicated by diagonal lines in FIG. 1B.
It is formed where 2x to 2y and 4 overlap. In other words, the power supply voltage V p is applied to the electrodes 2x and 2y, but since the value of V p is set higher than the threshold voltage V T of the MOS-FET, there is an inverted voltage immediately below the electrodes 2x and 2y. resulting in layer 10, 2x, 2y and 1
The capacitance with 0 as the electrode and 6 as the dielectric is used as the capacitance of Csa to Csc.
さて、上述のような従来技術においては次のよ
うな問題点を有している。 Now, the above-mentioned conventional technology has the following problems.
Ｃsa〜Ｃsbの容量値は、第１図Ｂから明らかな
ように、薄い酸化膜６と厚い酸化膜５の領域を分
けるパターン４と、多結晶シリコンのパターンで
ある２ｘ，２ｙの重なり面積で決定される。 As is clear from FIG. 1B, the capacitance values of C sa to C sb are determined by the overlap area of the pattern 4 that separates the thin oxide film 6 and thick oxide film 5 and the polycrystalline silicon patterns 2x and 2y. determined by
これらのパターン形成は通常の写真蝕刻法（フ
オトエツチング）によつてなされるが、パターン
４と、パターン２ｘ，２ｙは互いに異なる工程で
形成されるため相互のマスク位置合せ誤差を生じ
る。たとえば、第１図Ｂにおいて、多結晶シリコ
ンのパターン２ａ〜２ｃ，２ｘ，２ｙがパターン
４に対して、右方向にズレたとすると、Ｃscの容
量値は大きくなるが、Ｃsbの容量値は小さくな
り、所定の安定な動作が得られなくなる。したが
つてメモリ回路パターンの設計においてはこのズ
レを考慮して、ＣSの容量を大きく設計しておく
必要があり、メモリ回路自体の占有面積が必要以
上に大きくなる欠点を生じる。 These patterns are formed by ordinary photoetching, but since pattern 4 and patterns 2x and 2y are formed in different steps, mutual mask alignment errors occur. For example, in FIG. 1B, if polycrystalline silicon patterns 2a to 2c, 2x, and 2y are shifted to the right with respect to pattern 4, the capacitance value of C sc becomes large, but the capacitance value of C sb becomes becomes smaller, and a predetermined stable operation cannot be obtained. Therefore, in designing the memory circuit pattern, it is necessary to take this deviation into account and design the capacitance of C S to be large, which results in the drawback that the area occupied by the memory circuit itself becomes larger than necessary.
またさらに、パターン４を最近拡く用いられて
いる部分酸化法（LOCOS）によつて形成する場
合には、第１図Ｂに示したメモリ回路間の間隙１
１が拡まり、結果としてメモリ回路の占有面積を
大きく設計せざるを得ないという、前述と同様の
問題を生じる。 Furthermore, when the pattern 4 is formed by the partial oxidation method (LOCOS) which has been widely used recently, the gap 1 between the memory circuits shown in FIG.
1 is expanded, and as a result, the same problem as described above arises in that the area occupied by the memory circuit must be designed to be large.
本発明の目的は、メモリ回路の記憶容量のＣs
の面積すなわち容量値を、１回の写真蝕刻工程で
自己整合的に定まるようにし、占有面積の小さい
メモリ回路を提供することである。 An object of the present invention is to increase the storage capacity C s of a memory circuit.
An object of the present invention is to provide a memory circuit which occupies a small area by determining the area, that is, the capacitance value, in a self-aligning manner by one photolithography process.
以下本発明の詳細を実施例によつて説明する。 The details of the present invention will be explained below with reference to Examples.
第２図は、本発明になる実施例の平面図を示す
ものである。同図から分るようにパターン的には
４がデータ線１に沿つた方向ではメモリ回路毎に
分離されていないこと、記憶容量の一方の電極と
なる多結晶シリコンが、２ｘ〜２ｚのように各メ
モリ回路毎に分離されていることが従来技術の場
合と異なる。 FIG. 2 shows a plan view of an embodiment of the present invention. As can be seen from the figure, in terms of patterns, 4 is not separated for each memory circuit in the direction along data line 1, and the polycrystalline silicon that becomes one electrode of the storage capacitor is similar to 2x to 2z. This differs from the prior art in that each memory circuit is separated.
第３図Ｃは本実施例の断面構造を示しており、
多結晶シリコン２ｙ，２ｚの間隙のシリコン基板
表面にチヤネル・ストツパとして基板と同タイプ
の1016〜1017cm-3程度のＰ形不純物層を形成して
ある。 FIG. 3C shows the cross-sectional structure of this example,
A P-type impurity layer of about 10 16 to 10 17 cm -3 of the same type as the substrate is formed as a channel stopper on the surface of the silicon substrate in the gap between the polycrystalline silicon 2y and 2z.
このような構造においては、２ｙと２ｚの間隙
部では、１をゲート金属、８をゲート絶縁膜とす
る寄生MOS−FETが形成されるが、、ゲート直下
の基板濃度が1016〜1017cm-3と高く、また８の膜
は5000〜10000Åと充分厚いので寄生MOS−FET
のしきい電圧は１に印加される電圧に比べ充分高
くなり、この部分に電流通路を生じることなく、
容量ＣsbとＣscは完全に分離される。本実施例に
よれば、記憶容量Ｃsの値はパターン４で決まる
一組の対辺と、パターン２ｘ，２ｙ，２ｚで決ま
るもう一組の対応で囲まれる長方形の面積で決ま
るため、マスクの位置合せ誤差によつて値が変化
することはない。 In such a structure, a parasitic MOS-FET with 1 as a gate metal and 8 as a gate insulating film is formed in the gap between 2y and 2z, but if the substrate concentration directly under the gate is 10 16 to 10 17 cm -3 , which is high, and the film of 8 is sufficiently thick at 5000 to 10000 Å, so the parasitic MOS-FET
The threshold voltage of 1 is sufficiently high compared to the voltage applied to 1, and no current path occurs in this part.
Capacitances C sb and C sc are completely separated. According to this embodiment, the value of the storage capacity C s is determined by the area of a rectangle surrounded by one set of opposite sides determined by pattern 4 and another set of correspondence determined by patterns 2x, 2y, and 2z. The value does not change due to alignment errors.
以下、第３図にしたがつて本実施例の製造方法
について述べよう。 The manufacturing method of this embodiment will be described below with reference to FIG.
不純物濃度1014〜1016cm-3程度のＰ形シリコン
基板の主表面に、部分酸化法あるいは通常のシリ
コン酸化膜を形成した後の写真蝕刻法によつてパ
ターン４を形成する。次いでゲート絶縁膜となる
500〜1000Å程度のシリコン酸化膜６を形成し、
その表面に多結晶シリコン２を形成する。写真蝕
刻法により、多結晶シリコン２に２ａ〜２ｃ，２
ｘ，２ｚのパターンを形成する。フオトレジスト
膜１２を形成し、２ｙ，２ｚの間隙部にフオトレ
ジスト膜の窓を形成する。 A pattern 4 is formed on the main surface of a P-type silicon substrate with an impurity concentration of about 10 14 to 10 16 cm -3 by a partial oxidation method or a photolithography method after forming an ordinary silicon oxide film. Next becomes the gate insulating film
A silicon oxide film 6 of about 500 to 1000 Å is formed,
Polycrystalline silicon 2 is formed on the surface. 2a to 2c, 2 on polycrystalline silicon 2 by photolithography.
Form a pattern of x, 2z. A photoresist film 12 is formed, and a window of the photoresist film is formed in the gap between 2y and 2z.
この窓を通してシリコン基板３と同タイプの不
純物たとえばボロン１３をイオン注入法により注
入し、等価的表面濃度1016〜1017cm-3のチヤネ
ル・ストツパとしてのＰ形不純物層１４を形成す
る。（第３図Ａ）
次いでフオトレジスト１２を除去後、再びフオ
トレジスト１５を形成し、２ｙ，２ｚの間隙部を
おおい、その他の部分のシリコン酸化膜６を除去
し、通常の拡散法によつて、基板３と異なるタイ
プの不純物たとえば、リン、ひ素などの拡散を行
ない、高濃度N+層７を形成する。このとき２
ｙ，２ｚの間隙部ではシリコン酸化膜６がマスク
として作用し拡散されない。（第３図Ｂ）
その後は通常のシリコンゲート型MOS−FET
プロセスと同様に、5000〜10000Å程度のリンガ
ラス８を形成し、層間連絡孔９を形成した後、
Al層１を形成する。（第３図Ｃ）
ゲート電極２ｙと２ｚの間の絶縁は不純物層１
４に反転層が形成されないようにすることにより
行なわれる。一般に、反転層形成のためのしきい
値は不純物層１４の不純物濃度および不純物層１
４上の絶縁膜の厚さ（今の例ではシリコン酸化膜
６とゲート酸化膜８の厚さの和）が大きい程、大
となる。したがつてAl層１に印加される電圧の
最大値よりもこのしきい値が大きくなるように、
不純物層１４の濃度および絶縁膜８の厚さを定め
ることにより、行方向に隣接する容量間の絶縁が
可能となる。 Through this window, an impurity of the same type as that of the silicon substrate 3, such as boron 13, is implanted by ion implantation to form a P-type impurity layer 14 as a channel stopper with an equivalent surface concentration of 10 16 to 10 17 cm -3 . (FIG. 3A) Next, after removing the photoresist 12, a photoresist 15 is formed again to cover the gaps 2y and 2z, and the silicon oxide film 6 in other parts is removed, using a normal diffusion method. , a type of impurity different from that of the substrate 3, such as phosphorus or arsenic, is diffused to form a high concentration N + layer 7. At this time 2
In the gap between y and 2z, the silicon oxide film 6 acts as a mask and is not diffused. (Figure 3B) After that, it is a normal silicon gate type MOS-FET.
Similar to the process, after forming phosphorus glass 8 of about 5000 to 10000 Å and forming interlayer communication holes 9,
An Al layer 1 is formed. (Figure 3C) The insulation between the gate electrodes 2y and 2z is the impurity layer 1.
This is done by preventing the formation of an inversion layer on the 4th layer. Generally, the threshold value for forming an inversion layer is the impurity concentration of the impurity layer 14 and the impurity layer 1
The larger the thickness of the insulating film on 4 (in this example, the sum of the thicknesses of silicon oxide film 6 and gate oxide film 8) becomes larger. Therefore, so that this threshold value is larger than the maximum value of the voltage applied to the Al layer 1,
By determining the concentration of the impurity layer 14 and the thickness of the insulating film 8, it is possible to insulate capacitors adjacent in the row direction.
上記製造方法においては、１４と７の形成工程
を入れ替える事、また７の拡散をイオン注入法に
よつて形成する事は容易に可能である。 In the above manufacturing method, it is easily possible to interchange the formation steps of 14 and 7, and to form the diffusion of 7 by ion implantation.
またさらに、１４の形成工程において１２をマ
スクとしてイオン注入法を用いたが、特に１２を
用いず、多結晶シリコン２ａ〜２ｂ，２ｙ，２ｚ
をマスクとしたイオン注入法によつて１４を形成
することも可能である。このときN+拡散層７と
１４が重なる部分において、接合容量値が増大す
るが、７の拡散深さを１４のそれに比べ大きく設
定しておけば、この問題は解決できる。 Furthermore, in the step of forming 14, an ion implantation method was used using 12 as a mask, but 12 was not used and polycrystalline silicon 2a to 2b, 2y, 2z
It is also possible to form 14 by an ion implantation method using as a mask. At this time, the junction capacitance value increases in the portion where N + diffusion layers 7 and 14 overlap, but this problem can be solved by setting the diffusion depth of 7 to be larger than that of 14.
第４図は本発明の他の実施例を説明する図であ
る。第３図に示した実施例とは、チヤネル・スト
ツパとしてのＰ形不純物層１４をMOS−FETの
しきい電圧制御用のイオン注入（チヤネル・ドー
プ）と同時に形成する点が異なり、パターン的に
は第２図に示したものと同一である。 FIG. 4 is a diagram illustrating another embodiment of the present invention. The difference from the embodiment shown in FIG. 3 is that the P-type impurity layer 14 as a channel stopper is formed at the same time as the ion implantation (channel doping) for controlling the threshold voltage of the MOS-FET. is the same as shown in FIG.
まず、第３図と同様にしてパターン４を形成し
たのち、ゲート絶縁膜としてのシリコン酸化膜６
の形成前あるいは形成後にＰ形シリコン基板３と
同タイプの不純物たとえばボロンのイオン注入に
よつて、チヤネルドープ、およびチヤネルストツ
パとして、の等価的表面濃度1015〜1016程度のＰ
形不純物層１４を形成する。（第４図Ａ）その後
は、第３図と同様に、第４図Ｂを経て第４図Ｃに
至る。本実施例では、ゲート電極３ｂ，３ｃの間
に形成される不純物層１４に反転層が形成されな
いように、ここの不純物濃度および絶縁膜８の厚
さを定めるのは第１の実施例と同じである。な
お、本実施例では、ゲート電極３ｂ，３ｃの下に
同じ不純物層が形成されるが、ここにはシリコン
酸化膜６の厚さが薄いので、反転層が形成される
ため、容量として使用する上で問題はない。 First, a pattern 4 is formed in the same manner as in FIG. 3, and then a silicon oxide film 6 is formed as a gate insulating film.
Before or after the formation of the P-type silicon substrate 3, an impurity of the same type as the P type silicon substrate 3, such as boron , is ion-implanted to perform channel doping and as a channel stopper.
A shaped impurity layer 14 is formed. (FIG. 4A) After that, similarly to FIG. 3, the process goes through FIG. 4B and then reaches FIG. 4C. In this embodiment, the impurity concentration and the thickness of the insulating film 8 are determined in the same manner as in the first embodiment so that an inversion layer is not formed in the impurity layer 14 formed between the gate electrodes 3b and 3c. It is. In this embodiment, the same impurity layer is formed under the gate electrodes 3b and 3c, but since the silicon oxide film 6 is thin here, an inversion layer is formed and used as a capacitor. There is no problem with the above.
以上述べたとおり、本発明によれば、列方向に
はゲート電極形成前に形成された厚い酸化膜によ
るアイソレーシヨンを用い、さらに、列方向に連
なつた電極を用いることにより、厚い酸化膜形成
用のマスク又はゲート電極形成用のマスクが列方
向にずれても容量の変動はない。さらに、また、
行方向には、ゲート電極形成後に形成された絶縁
膜および不純物層を用いて、アイソレーシヨンす
るため、ゲート電極形成用のマスクの位置が行方
向にずれても、容量の変動がなくなる。 As described above, according to the present invention, isolation by a thick oxide film formed before forming gate electrodes is used in the column direction, and by using electrodes connected in the column direction, a thick oxide film is formed. Even if the mask for formation or the mask for gate electrode formation is shifted in the column direction, the capacitance does not change. Furthermore, also
In the row direction, isolation is achieved using the insulating film and impurity layer formed after the gate electrode is formed, so even if the position of the mask for forming the gate electrode is shifted in the row direction, there is no variation in capacitance.
以上述べたように本発明によれば、従来技術で
問題となつた、マスク位置合せ誤差によつてメモ
リ回路の記憶容量ＣSの値が変化することはなく
常に必要十分の条件でＣSの設計をしておけばよ
い。また部分酸化法のプロセスを用いたとしても
ＣSの容量面積の減少の割合が従来技術に比べ少
なくなる。 As described above, according to the present invention, the value of the storage capacity C S of the memory circuit does not change due to mask alignment error, which was a problem with the prior art, and the value of C S is always maintained under necessary and sufficient conditions. All you have to do is design it. Furthermore, even if a partial oxidation process is used, the rate of decrease in the capacitance area of C S is smaller than in the prior art.
これらの効果によつて、メモリ回路１ビツト当
りの占有面積を従来技術に比べ約２〜３割小さく
することが可能となる。 These effects make it possible to reduce the area occupied by one bit of the memory circuit by about 20 to 30 percent compared to the prior art.
なお本発明の適用範囲はここで述べた実施例に
限定されるものでなく、本発明の思想を逸脱しな
い範囲で種々適用可能なことは言うまでもない。
たとえば、実施例ではｎチヤネル形MOS−FET
を例にしたが、Ｐチヤネル形MOS−FETにも勿
論適用可能であり、またゲート電極は多結晶シリ
コン、タングステン、モリブデンあるいはこれら
と積層したものでもかまわない。 It goes without saying that the scope of application of the present invention is not limited to the embodiments described here, and that various applications can be made without departing from the spirit of the present invention.
For example, in the embodiment, an n-channel MOS-FET
Although the present invention is taken as an example, it is of course applicable to a P-channel type MOS-FET, and the gate electrode may be made of polycrystalline silicon, tungsten, molybdenum, or a stack of these.
第１図は従来技術を説明する図、第２図〜第４
図は実施例を説明する図である。
１……データ線（Al）、２……ワード線（多結
晶シリコン）、３……シリコン基板、４……フイ
ールドパターン、５……厚いシリコン酸化膜、６
……薄いシリコン酸化膜、７……N+拡散層、８
……リンガラス（PSG）、９……層間連絡孔、１
０……反転層、１１……間隙長、１２，１５……
フオトレジスト膜、１３，１６……イオン注入
源、１４……Ｐ形不純物層、Ｑ……MOS−
FET、ＣS……記憶容量、ＣD……データ線容
量。
Figure 1 is a diagram explaining the prior art, Figures 2 to 4
The figure is a diagram explaining an example. 1... Data line (Al), 2... Word line (polycrystalline silicon), 3... Silicon substrate, 4... Field pattern, 5... Thick silicon oxide film, 6
...Thin silicon oxide film, 7...N + diffusion layer, 8
... Ring glass (PSG), 9 ... Interlayer communication hole, 1
0... Inversion layer, 11... Gap length, 12, 15...
Photoresist film, 13, 16...Ion implantation source, 14...P type impurity layer, Q...MOS-
FET, C S ... storage capacity, C D ... data line capacity.
Claims (1)
数の容量からなり、各容量は、該半導体基体表面
上に形成された薄い酸化膜と、該酸化膜上に形成
された電極と、該電極下の半導体基板表面に形成
された反転層とからなり、該電極と反転層を各容
量の二つの電極として利用するように構成されて
いる半導体装置の製造方法において、 列方向に隣接する二つの容量の形成領域間の基
板表面に厚い酸化膜を形成し、その形成後、各容
量の形成領域の基板表面に薄い酸化膜を形成し、 列方向に隣接する容量のそれぞれの形成領域の
薄い酸化膜上およびこれらの間の厚い酸化膜上に
延在して電極形成用の導電膜を各列ごとに分離し
て形成し、その後、行方向に隣接する二つの容量
形成領域間の基板表面に基板の不純物と同じ導電
性を有しそれより濃度の大きな不純物層を形成
し、その後、該不純物層上方に、該不純物層に反
転層が形成されないようにするのに必要な厚さの
絶縁膜を形成することを特徴とする半導体装置の
製造方法。[Claims] 1 Consists of a plurality of capacitors arranged in a two-dimensional matrix on a semiconductor substrate, each capacitor comprising a thin oxide film formed on the surface of the semiconductor substrate and a thin oxide film formed on the oxide film. In a method for manufacturing a semiconductor device, the semiconductor device is configured to include an electrode and an inversion layer formed on a surface of a semiconductor substrate under the electrode, and the electrode and the inversion layer are used as two electrodes of each capacitor. A thick oxide film is formed on the substrate surface between two capacitance formation regions adjacent in the column direction, and after that formation, a thin oxide film is formed on the substrate surface of each capacitance formation region, and each of the capacitances adjacent in the column direction is A conductive film for forming electrodes is formed separately for each column by extending on the thin oxide film in the formation region and on the thick oxide film between these, and then two capacitors are formed adjacent to each other in the row direction. Necessary to form an impurity layer on the substrate surface between regions that has the same conductivity as the impurity of the substrate and has a higher concentration, and then to prevent an inversion layer from being formed above the impurity layer. 1. A method of manufacturing a semiconductor device, comprising forming an insulating film with a thickness of 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7451976A JPS53985A (en) | 1976-06-25 | 1976-06-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7451976A JPS53985A (en) | 1976-06-25 | 1976-06-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53985A JPS53985A (en) | 1978-01-07 |
| JPS6124829B2 true JPS6124829B2 (en) | 1986-06-12 |
Family
ID=13549644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7451976A Granted JPS53985A (en) | 1976-06-25 | 1976-06-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS53985A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60143663A (en) * | 1984-10-24 | 1985-07-29 | Hitachi Ltd | semiconductor storage device |
-
1976
- 1976-06-25 JP JP7451976A patent/JPS53985A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53985A (en) | 1978-01-07 |
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