JPS6124868B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a facsimile receiver, and in particular, an object of the present invention is to accurately detect and decode an image signal from a compressed and transmitted facsimile signal.

In recent high-speed facsimile devices, the number of run lengths of character information obtained on the transmitter side is compressed and coded into a suitable binary code signal such as Modified Hoffmann MH code, and a separate code is generated for each line of this coded image signal. A coded line synchronization signal is inserted and transmitted to the receiver side, and the receiver side converts the coded image signal separated and extracted from the received signal into pulse train signals of a number equivalent to the number of run lengths of the original character information. I am trying to decode and record.
At that time, such facsimile devices use extremely high-speed transmission clocks or perform a two-dimensional encoding process called the lead coating method to further reduce transmission time. I'm trying to shorten it. Therefore, in order to process and decode the facsimile signals transmitted at very high speeds in this way in real time at the receiver side, an extremely fast clock must be used, which is not possible with current circuit technology. This cannot be achieved easily from the viewpoint of reducing manufacturing costs. For this reason, many current facsimile receivers use a so-called decoding buffer method in which the facsimile signals transmitted from the transmitter are temporarily stored in a suitable buffer memory, and then the facsimile signals are sequentially read out and decoded. We are hiring.

However, in the facsimile signal transmitted from the transmitter side, there is a signal similar to the coded image signal, for example.
A line synchronization signal such as [01111111] consisting of a bit "0" followed by 7 bits "1" is inserted, and an identification code to distinguish this synchronization signal from the image signal is included in the image signal. It is now being inserted. This identification code is such that when 5 or more bits of "1" continue as in [0011111101] in a coded image signal, there is a 1-bit "0" between the 5th bit "1" and the next bit. is inserted as [00111110101], and this "0" is generally called a zero insertion.

For this reason, conventional facsimile receivers extract and decode the image signal from the received signal by detecting the above-mentioned zero insertion, but with this method, the zero insertion is detected once. There was a drawback that if a mistake was made, it would interfere with the subsequent decoding operation.

Therefore, the present invention proposes a facsimile receiver that eliminates these drawbacks, and the details thereof will be explained below with reference to the drawings.

FIG. 1 shows a schematic configuration of essential parts of an embodiment of the facsimile receiver of the present invention. In the same figure, 1
is an input terminal into which the facsimile input signal A transmitted from the transmitter side is introduced, and this signal A is sequentially introduced into the first sequence controller 2 by the clock pulse φ ₁ synchronized therewith, and the above-mentioned φ ₁ The first D flip-flop 3, which is driven by the inverted clock pulse ₁ , delays the phase by half a bit (see Figure 2 A') and outputs the RAM.
is led as an input to a first memory 4 consisting of.

The write pulse D of this first memory 4 is the second pulse D.
It is created by 3D flip-flops 9 and 10 and AND gate 11, but at that time, its 2D
The other clock pulse _φ2 applied to the flip-flop 9 is selected to have a sufficiently higher frequency than the other clock pulse _φ1 .

The write pulse D from the AND gate 11 is supplied as a count input to the first counter 7,
Further, an inverted output D' of the pulse D by the inverter 12 is applied as a switching signal to the multiplexer 6 and a write/read control signal to the first memory 4 described above and the second memory 5 described later. That is, when the inverter output D' is at a low level, the multiplexer 6 transfers the output F of the first counter 7 for writing address designation to the first and second memories 4 and 5.
The output G of the second counter 8 for read address designation is derived as the input H when the inverter output D' is at a high level. Further, the first and second memories 4 and 5 are switched to be in a write mode when the inverter output D' is at a low level, and to be in a read mode when it is at a high level.

The first sequence controller 2 consists of a microprocessor, and determines whether the facsimile input signals A successively introduced therein are a coded image signal or a line synchronization signal. In other words, the line synchronization signal is set to [01111111] as mentioned above,
Further, assuming that the image signal is subjected to the above-mentioned zero insertion, the controller 2
monitors the following “1” every time “1” appears in its input signal A, and if the next 6th bit after five consecutive “1”s is also “1”, it is a line synchronization signal. If the 6th bit is "0", it is determined that it is zero insertion. When this controller 2 determines that it is a line synchronization signal, it derives an output B that is inverted to "1", that is, a high level, only during the last bit of the synchronization signal, that is, the 8th bit, and determines that it is a zero insertion. When the determination is made, an output C which is inverted to "0", that is, low level, is derived during the zero insertion period.

Therefore, if the facsimile input signal to terminal 1 is as shown in A in Figure 2, then
Outputs B and C of the sequence controller 2 are as shown in the figure. Since one of these outputs C is applied as a reset signal (reset at low level) to the second and third D flip-flops 9 and 10, the write pulse D from the AND gate 11 reaches zero insertion as shown in the figure. It will not occur in the corresponding period. For this reason, the first
The memory 4 stores a signal obtained by removing zero insertion from the facsimile input signal A, that is, [......
1111001111111……] will be stored.

On the other hand, the other output B of the first sequence controller 2 is led as an input to a second memory 5 consisting of a RAM, and the above-mentioned inverter output D' is applied to this second memory under the same write and read control as the first memory. Applied as a signal. Therefore, the second memory 5 stores a signal in which only the bit corresponding to the final bit of the synchronization signal in the facsimile signal A stored in the first memory 4 is "1" and all other bits are "0". [……0001000000000……
…] will be stored.

Next, 13 is an address comparator that compares the outputs F and G of the first and second counters 7 and 8, that is, the write address and the read address, and its output I is at a high level only when the above two addresses match. At other times, it is at a low level, and this output I is given to a second sequence controller 14 consisting of a microprocessor. This controller 14 controls the derivation of the reading pulse E using the comparator output I and a signal J which becomes high level when the image signal decoding circuit 15 described later is performing a decoding operation as control inputs. That is, when the signals I and J are both at a low level, the controller 14 determines that reading is possible and derives the reading pulse E, and when either of the signals I and J is at a high level, it is determined that reading is not possible. The determination is made and the derivation of the pulse E is prohibited. Therefore, as shown in FIG. 2, this read pulse E is not derived at regular intervals but intermittently. Note that this pulse E is selected to have a sufficiently higher frequency than the write pulse D.

The read pulse E from the second sequence controller 14 is introduced into the second counter 8, which sequentially specifies the read addresses of the first and second memories 4 and 5. For this reason, the above-mentioned signals [......1111001111111...] and [...] stored in the first and second memories 4 and 5, respectively.
...0001000000000......] are read out one bit at a time. Then, the output signal K of the first memory is introduced to the second sequence controller 14 and the image signal decoding circuit 15, and the output signal L of the second memory is introduced only to the controller 14.

The decoding circuit 15 includes memories for parallel conversion, decoding, and buffering, and obtains the output signal L of the second memory and decodes the image signal in the signal. That is, this circuit 15 converts a coded image signal representing a run length of character information into a serial pulse train signal of a number corresponding to the original run length, and stores the pulse train signal in a buffer memory within the circuit 15. be. At this time, this decoding operation is performed only on the image signal in the output signal K of the first memory, and is accomplished as follows. That is, the second sequence controller 14 detects six consecutive "1"s in the output signal K of the first memory, and detects six consecutive "1"s in the output signal L of the second memory at the timing of the sixth "1". When "1" is detected, it is determined that the previous signal is a line synchronization signal, and an output M (see FIG. 3) which goes high at the rising timing of the next bit is given to the decoding circuit 15. Thereby, this decoding circuit 15 sequentially decodes the image signal following the synchronizing signal in the output signal K of the first memory, starting from the first bit, and sequentially sends the pulse train signal derived thereby to the buffer memory described above. I put it away and go.

When the decoding circuit 15 performs decoding in this manner and pulses corresponding to the number of pixels in one line, for example 1728, are stored in the buffer memory, the second sequence controller 14 inverts the output M to a low level, and Therefore, the above decoding operation is stopped. Subsequently, when the second sequence controller 14 similarly detects the synchronization signal of the next line, it causes the next line following the synchronization signal to be decoded in exactly the same manner as described above, and also outputs the decoded signal of the previous line. That is, the aforementioned pulse train signal is read out from the buffer memory within the decoding circuit 15. For this reason, in this memory, writing for one line and reading from the previous line are performed at the same time, so two memory units each having a storage capacity for one line are provided, and writing and reading to each of them is performed. Although it is necessary to configure the decoding circuit 15 so that the decoding circuit 15 is configured in such a manner, such a configuration is already known, so further explanation of this point will be omitted. In addition,
The image signal is recorded by supplying the pulse train signal read out from the decoding circuit 15 to a recording means that can be a multi-stylus recording head or the like.

Incidentally, the decoding operations described above are cases where the decoding operations are performed normally, but when a malfunction occurs in the decoding, the following operations are performed. That is, in this case, while the decoding circuit 15 is performing the decoding operation, the second sequence controller 14
detects "1" in the output signal L of the second memory, so this controller determines that the decoding up to that point is an error and immediately inverts the output M to low level. , thereby stopping the decoding operation of the decoding circuit 15.
At the same time, the controller 14 gives an instruction N to the decoding circuit 15, thereby causing the first
After detecting "1" in the output signal K of the memory, that is, a line synchronization signal, the decode output of the line immediately before the synchronization signal, that is, the line that was decoded incorrectly, is not read out from the decoding circuit 15, but instead 1
The decoded output from the previous line is read and supplied to the storage means described above. At this time, the reason why the information on the same line is recorded twice in succession is because character information in facsimile is generally considered to be similar between two consecutive lines. In addition,
Since configuring the inside of the decoding circuit 15 in this manner can be easily realized by following the conventional technology, detailed explanation of this point will be omitted here.

As explained above, the facsimile receiver of the present invention sequentially stores facsimile input signals including a line synchronization signal and a coded image signal in the first memory means, and synchronizes with writing to the first memory means. When storing the image signal in the input signal, a predetermined 1-bit code is used, and when storing the line synchronization signal, a code different from that code is used as a second code.
The image signal is extracted and decoded from the input signal by sequentially writing data into the memory means and detecting a change in sign of each output signal read out later from the first and second memory means. Therefore, it is possible to achieve a reliable decoding operation with fewer malfunctions than in the conventional method in which the image signal is decoded by monitoring only the sign change of the facsimile input signal. Furthermore, in the present invention, when storing the facsimile input signal in the first memory means, the identification code such as zero insertion in the image signal is removed in advance and written, so that the output of the first memory means is When a signal is obtained and decoded, there is no possibility that a malfunction will occur due to the identification code, and therefore, a more reliable decoding operation can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of essential parts of an embodiment of the facsimile receiver of the present invention, and FIGS. 2 and 3 are time charts for explaining its operation.

Claims (1)

[Claims] 1. A facsimile signal received by a facsimile receiver that receives as input a facsimile signal in which a separately coded line synchronization signal is inserted for each line of an image signal in which the run length number of character information is binary coded. a first memory means for sequentially storing information in the facsimile signal; a first control means for detecting a line synchronization signal in the facsimile signal and an identification signal for distinguishing the synchronization signal from the image signal; When storing an image signal, predetermined 1-bit codes are sequentially stored, and when storing a line synchronization signal, a second memory means stores a code different from the above code, and the output of the first memory means a decoding means for obtaining the signal and deriving a pulse train signal corresponding to the run length number of the original character information, and comparing the write address and the read address of the first and second memory means, and depending on whether the two addresses match or do not match. The output signal from the decoding means and the output signal from the decoding means outputted in response to the decoding operation of the decoding means are used as control inputs, and the first and second
A second control means for controlling the derivation of a reading pulse of the memory means is provided, the first and second memory means are synchronized to perform write and read operations, and the control means is configured to control derivation of a reading pulse of the first memory means, and to perform a write and read operation in synchronization with the image signal in the output signal of the first memory means. The facsimile receiver is characterized in that the decoding means performs a decoding operation only when the decoding means is used.