JPS61255486A - Graphic processing unit - Google Patents

Abstract

PURPOSE:To eliminate noise and to correct a blurred part by synthesizing two patterns obtained by binary-coding a multi-value pattern obtained from the optical scanning with two different threshold values. CONSTITUTION:The multi-value signal (m) of a character pattern obtained from a photoelectric converting section and scanned is binary-coded at quantization circuits 10, 11 as binary-coding means set with two different threshold values and the result is stored in pattern memories 12, 13 respectively. The two character patterns are fed to a pattern synthesis circuit 14, where the patterns are synthesized by deciding one picture element bit depending on adjacent 8-bit, resulting that a character pattern without noise or blur is obtained and stored in a pattern memory 15.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a preprocessing part of an optical character reading device, etc., and particularly relates to a graphic processing device that removes writing frames and paper noise and compensates for blurred parts. It is something.

[Conventional technology]

Conventionally, the characters on a form that must be read by an optical character reader have various densities depending on factors such as the writing instrument and writing pressure in the case of handwritten characters, and factors such as the ink ribbon printing pressure level in the case of printed characters. did. In order to improve reading accuracy by taking into account characters of various densities, marks and sizes on the paper surface, etc.
An operation called "rescan reading" is performed in which the characters are binarized using different threshold values, read multiple times, and a final judgment character is output from the results.

[Problem that the invention seeks to solve]

In the conventional "rescan reading" method described above, binary patterns are obtained with different threshold values, but each pattern is not necessarily optimal for recognition. This example is the first
It is shown in Figure 5. FIG. 15(a) shows a character pattern obtained with a low threshold, and unnecessary noise other than the character pattern is added. FIG. 15(b) shows a character pattern obtained with a high threshold value, where some of the characters are faded and important information for character recognition is missing. In this way, for characters with noise or blurring, it is not possible to obtain an optimal character pattern with one threshold value, and even if multiple character patterns are obtained with different threshold values, each pattern has noise and blurring. There was blurring and it was very difficult to accurately recognize these character patterns. For this reason, accurate recognition using multiple patterns using different threshold values has been required.

[Means for solving problems]

In order to meet such demands, the present invention provides a reading means for optically scanning a detected pattern to obtain a multi-value pattern, and a reading means for optically scanning a detected pattern to obtain a multi-value pattern, and converting this multi-value pattern into ``0'' or ``1'' using a predetermined threshold.
A binarization means for converting into values and a synthesis means for synthesizing two patterns obtained by using two different threshold values are provided.

[Effect]

In the present invention, a binary pattern with two threshold values, a higher threshold value and a lower threshold value, is combined to create a pattern optimal for reading.

〔Example〕

Next, embodiments of the present invention will be described using FIGS. 1 to 14. FIG. 1 shows an embodiment of a graphic processing apparatus according to the present invention. A character pattern 1 written on a form, etc. is observed by a photoelectric conversion unit 2 as a reading means, preprocessed by a preprocessing unit 3, and normalized such as character size by a normalization unit 4. and sent to the feature extraction section 5. Feature extraction unit 5
Then, the determination unit 6 extracts various features effective for determination from the normalized character pattern, and compares and matches the character patterns stored in the character dictionary 7 prepared in advance with the character patterns input to the determination unit 6. The character with the most similar pattern is output as the determination result.

FIG. 2 is a system diagram showing the components of the preprocessing section 3 shown in FIG. 1. The multilevel signal m of the character pattern sent from the photoelectric converter 2 shown in FIG.
The values are converted into values and stored in the pattern memories 12 and 13, respectively. The two character patterns stored in the pattern memories 12 and 13 are further synthesized by a pattern synthesis circuit 14 serving as a synthesis means and stored in the pattern memory 15.

FIG. 3 shows the pattern memory 12, 13 and pattern synthesis circuit 14 of FIG. 2 in detail. flip flop 20
indicates one element (1 bit) of pattern memory 12 in FIG. 2, and latch 21 indicates one element of pattern memory 13. The flip-flop 20 receives a pattern signal a with a low threshold quantized by the quantizer 10, and the latch 21 receives a pattern signal f with a high threshold quantized by the quantizer 11 as the same clock signal. It is set at .

The input of the OR circuit 23 in the previous stage of the latch 21 is that the 8-bit information of 1 to 8 of the 3 meshes around one bit kO of the pattern memory 13 as shown in FIG.
This is the signal g that is ORed with 2.

Further, the clock signal q becomes the lock signal d, which is valid only when the binary pattern "1" is set in the flip-flop 20, that is, when the output signal C of the flip-flop 20 is "1", and the latch signal of the latch 21 It becomes i. In other words, since the latch 21 changes from "0" to "1" while the clock signal e is active, the "1" bits are successively transmitted to adjacent bits by the clock signal e during a predetermined period of time. A desired character pattern as shown in the pattern memory 15 of FIG. 2 is obtained as the output signal j. This operation will be explained using a simple example shown in FIG.

Similar to the pattern in FIG. 15(a), the pattern in FIG. 5(a) is set in the pattern memory 12 as a pattern quantized with a low threshold value, and the flip-flop 20 in FIG. 3 constitutes one bit of the pattern. do. Similarly to the pattern shown in FIG. 15), the pattern shown in the fifth example) is set in the pattern memory 13 as a pattern quantized with a high threshold value, and the latch 21 shown in FIG. 3 constitutes one bit of the pattern.

The pattern shown in Figure 5(C) is as shown in Figures 5(a) and (b).
This is the final pattern obtained by combining the patterns.

6 to 11 are timing charts showing the operation of the pattern synthesis circuit 14 until the patterns of FIGS. 5(a) and 5(b) are synthesized to obtain the pattern of FIG. 5(C). First, the pattern shown in FIG. 5(a) is set in the flip-flop 20 by the clock signal shown in FIG. 6(a). 7 to 11, A shown in FIG. 5,
The operations of five points B, C, D, and E are shown, and each figure (a) is a low threshold pattern signal a that is input to the flip-flop 20, and each figure (bl is the low threshold pattern signal a that is output from the flip-flop 20). Signal C1 Each figure (C) is the latch signal i output from the OR circuit 25, each ffl (dl is the OR circuit 2
3, the pattern signal f at a high threshold is input to each figure (e
) shows the signal g output from the OR circuit 22, and each figure (f) shows the pattern signal j output from the latch 21.

As can be seen from the pattern in FIG. 5(a), the output signal C of the flip-flop 20 becomes rOJ only in FIG. 9, which shows the 0-point operation. The output signal C from the flip-flop 20 becomes an input to an AND circuit 24. A clock signal e shown in FIG. 6(b) is also input to the AND circuit 24. As mentioned above, since the clock signal e is ANDed with the previously sent output signal C of the flip-flop 20 in the AND circuit 24, in the pattern quantized with a low threshold shown in FIG. 5(a), The latch 21 can latch the input signal only at the "1" bit. In other words, the "0" part of the pattern in Figure 5(a) is the latch 2.
1 latch operation is prohibited. Each point A1 to E1 of the pattern in Fig. 5 (bl) is the point A-
Since it corresponds to E, out of each point A1 to E1, A1. B
1. Latch input is possible for each point Di and El, but C
Latch input is prohibited for one point. The input signal of the latch 21 is a signal obtained by inputting a pattern quantized with a high threshold value to the OR circuit 23 as a pattern signal f, and thereby obtaining the output signal j of the latch 21.

Looking at the pattern signal f, Fig. 8 (d
) only the pattern signal f is "1", and the point A, C-E
Figures 7(d) and 9(d) to 11(d) showing points
Since the pattern signal f is "0", "1" is latched only at the B1 point in FIG. Since the signal g is an ORed signal of 1 to 8, when one launch bit becomes "1", the surrounding 8 bits become "1".
1” may be latched. Since the latch signal i of the latch 21 is ANDed with the output signal C of the flip-flop 20 as described above, it is controlled according to the pattern shown in FIG. 5(a).

The 01 point shown in FIG. 5(b) is a bit included in the 8 bits surrounding the B1 point, and is also the "1" part of the pattern shown in FIG. 5(a), so the latch 21 of the 01 point teeth"
It is latched from "0" to "1". When the 01 point becomes "1", the 8 bits around the 01 point may change from "0" to "1", and similarly to the above, the 81 point becomes "1".

In this way, the "1" bit propagates to the 8-bit points around one point one after another (however, for point C1, which is the 8-bit point around the 81st point, in the pattern of Fig. 5(a),
Since the bit is "0", the latch clock signal d is prohibited as described above, so it does not become "1". Regarding point A1, the "1" bit does not propagate into the surrounding 8 bits, and remains as a "0" bit.

Three timings T1. in the timing charts of FIGS. 6 to 11. T2. FIGS. 12, 13, and 14 show the propagation of the "1" pattern at each time of T3. In FIGS. 12 to 14, each (a) shows a pattern set in the latch 21 at each time.

The pattern in Fig. 12 (ta) showing the pattern at time T1 shows the pattern itself that has been quantized with a high threshold value set in the latch 21, and the x mark in the pattern in Fig. 12 (ta) shows the pattern at the next timing. ” indicates a bit that can be set to “1”, and a circle indicates a bit that can latch “1”. Therefore, only the point where the X mark and the O mark overlap becomes "1" at the next timing, and this is the thirteenth (a) pattern showing the pattern at time T2.

Similarly, the point where the X and O marks overlap in the pattern shown in Figure 13) indicates a pattern that becomes "1" at the next timing, and the result is Figure 14 (a) which shows the pattern at time T3. This is the pattern.

In the pattern of FIG. 14(b), there are no longer any points where the x marks and the ○ marks overlap, indicating that the combination of the patterns has been completed.

In this way, it is possible to remove noise and compensate for blurred parts. Further, this embodiment is effective not only for the above-mentioned character recognition device but also for general graphic processing devices, image processing devices, and the like.

〔Effect of the invention〕

As explained above, the present invention includes a reading means for optically scanning a detected pattern to obtain a multi-value pattern, and a reading means for optically scanning a detected pattern to obtain a multi-value pattern;
By providing a value converting means and a synthesizing means for synthesizing two patterns obtained by two different threshold values,
Since noise can be removed and blurred parts can be compensated for, it is possible to obtain a character pattern that is optimal for character recognition.

[Brief explanation of drawings]

Fig. 1 is a system diagram showing an embodiment of the graphic processing device according to the present invention, Fig. 2 is a system diagram showing the preprocessing section that constitutes this, and Fig. 3 is the pattern memory and pattern synthesis circuit of the preprocessing section. FIG. 4 is a bit pattern diagram, FIG. 5 is a pattern diagram showing a character pattern, FIGS. 6 to 11 are timing charts showing the operation of the pattern synthesis circuit, and FIG.
FIGS. 2 to 14 are pattern diagrams corresponding to time, and FIG. 15 is a pattern diagram for explaining a conventional graphic processing device. 1... Character pattern, 2... Photoelectric conversion section, 3...
. . . Preprocessing section, 4. . . Normalization section, 5. . . Feature extraction section, 6. . . Determination section, 7. . . Character dictionary, 10
．． 11...Quantization circuit, 12.13.15...
Pattern memory, 14...Pattern synthesis circuit, 20
...Flip-flop, 21...Latch, 22
．． 23゜25...OR circuit, 24...AND circuit.

Claims (1)

[Claims] A reading means that optically scans the detected pattern to obtain a multi-value pattern, a binarization means that binarizes this multi-value pattern into "0" or "1" using a predetermined threshold value, and two different threshold values. 1. A graphic processing device comprising: a synthesizing means for synthesizing two patterns obtained by the above.