JPS61258480A - Junction type field effect transistor manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a junction field effect transistor with a self-aligned gate having a layer of semiconductor material with anisotropic etching properties, and to a method for manufacturing the same.

[Prior Art] Junction field effect transistors with self-aligned gates are described in literature (for example, IEEE 1ectronD
EDL-51, No. 7, January 1984, pp. 285-281). However, in the area around the source and gate contacts it has an unfavorable current distribution, resulting in high parasitic resistance and limiting the transconductance of the device.

Self-aligning means that the position of the gate between the source and drain does not need to be determined by a mask alignment process. Since the need for critical alignment processes is eliminated, self-aligned gates allow a substantial reduction in the contact spacing of the transistor, thus improving the characteristics of the transistor. In order to fabricate junction field effect transistors with self-aligned gates, semiconductor layers with anisotropic etching properties are required. The effect of anisotropy must be large. It is facilitated by a suitable crystal structure. Qa, As.

Semiconductors consisting of in and P and having a zinc blend crystal structure are well suited for this purpose. With an anisotropic etchant and appropriate crystal orientation structure for the etch mask, overhanging copper planes, or slanted sidewalls, are formed because different amounts of material are etched away in different crystal orientations (Journal o
f crysta+GrOWth 58.1982,
409-41G). This is especially true for the ■-v family or ■-■
This is remarkable in group compound semiconductors.

Problem to be Solved by the Invention It is therefore an object of the invention to provide a junction field effect transistor of the above type with high transconductance.

[Means for Solving the Problem] The object is to provide a junction type in which the gate contact is provided in a recess in a layer of semiconductor material with anisotropic etching properties, and the source and drain contacts are formed on the surface of said layer. Achieved by field effect transistors. Advantageous embodiments of the invention are set out in claims 2 and 3. Further, a method for manufacturing a transistor according to the present invention is described in claim 4.

[Advantage of the invention 1] An advantage of the invention is that the recessed gate produces a favorable current distribution in the source and drain contacts, which also improves the transconductance of the transistor.

[Example] Hereinafter, the structure and manufacturing method of the transistor of the present invention will be described in detail with reference to the accompanying drawings. The individual manufacturing steps for manufacturing a junction field effect transistor according to the invention are illustrated in FIGS. 1-4 and 6.

As usual, the transistors are not manufactured separately, but as a whole series on a wafer. However, in the following - by way of example it will be described as a single II. FIG. 1 shows an epitaxially deposited n on a semi-insulating semiconductor substrate 2.
A type semiconductor layer 1 is shown. This semi-insulating semiconductor substrate 2
is made of, for example, indium phosphide InP doped with Fe.

The n-type semiconductor layer 1 is made of n-type indium gallium arsenide I nGa doped with zinc, for example, with lattice matching with the substrate 2.
As a favor. The gate region 5 is selectively doped p-type with zinc Zn through an opening in the surface silicon nitride (Si3N+) diffusion mask 3. The gate region 5 becomes wider than the opening of the diffusion mask 3 due to the lateral diffusion effect.

In the next step (Figure 2), H2804-H20
2-H20 is used as an etching agent for anisotropic etching, and diffusion mask 3 is used as an etching mask. The semiconductor WJ1 has a zinc blend type crystal structure. The crystal orientation must be determined so that the (100) plane of the semiconductor layer 1 is the surface facing the etching mask 3, and the [011] direction is parallel to the longitudinal axis of the opening 4 of the slit-type mask. Only in this arrangement can the side surfaces 7 be formed by anisotropic etching. The etching takes place only in the p-doped region 5.

After removing the etching mask 3, a metal layer is deposited vertically on the wafer in a CF4 plasma to form the contacts. This is AU-CP3 alloy, pure AL1
It has a surface. The sides of the overhang create a break 9 in the metal layer, as shown in FIG. 3, which divides the metal layer into a source 10, drain 11 and gate 12.

In a second etching step (FIG. 4), which does not have to be anisotropic, the conductive connection between the source 10 and the drain 11 is interrupted in the p-doped region 5, the metal layer 10.11.12 being Used as a mask.

FIG. 5 shows an axially symmetrical junction field effect transistor.

If the metal layer is deposited at an angle rather than perpendicular to the surface of the semiconductor layer, an asymmetrical arrangement of the source, drain and gate contacts is obtained. In the device shown in FIG. 6, the gate contact portion 12 is close to the source contact portion 10. In this way, the parasitic resistance in the source and gate regions can be further reduced, thus improving the transconductance.

In the embodiments described above, an n-type semiconductor layer 1 and a p-type doped region 5 were used. In principle, it is possible to reverse the conductivity type. However, this has the disadvantage that the carrier transmission characteristics in the p-type channel are poor, which adversely affects the characteristics of the transistor. However, it is of course possible to use the two types if they are used as a complementary pair in a suitable circuit arrangement.

[Brief explanation of the drawing]

1, 2, 3, and 4 show cross-sectional views at each stage of the fabrication process of the transistor of the present invention, and FIG. 5 is a partial top view of the device of FIG. 4, FIG. 6 is a cross-sectional view of the device deposited from an oblique direction. DESCRIPTION OF SYMBOLS 1... Semiconductor layer, 2... 1 semi-insulating semiconductor substrate, 3
. . . mask, 4 . . . mask opening, 5 . . . diffusion region, 10 . . . source contact portion, 11 .

Claims (4)

[Claims] (1) A junction type with a self-aligned gate, characterized in that the gate contact is provided in a recess in a layer of semiconductor material with anisotropic etching properties, and the source and drain contacts are formed on the surface of said layer. Field effect transistor. (2) A junction field effect transistor according to claim 1, characterized in that a semiconductor material layer with anisotropic etching characteristics is grown on a semi-insulating layer in a lattice-matched manner. (3) A junction field effect transistor according to claim 2, characterized in that the semiconductor material layer with anisotropic etching characteristics is made of gallium indium arsenide, and the semi-insulating layer is made of indium phosphide. (4) A method for manufacturing a junction field effect transistor having a self-aligned gate having a semiconductor material layer with anisotropic etching characteristics, in which a lattice is aligned on the semi-insulating layer and the (100) plane is parallel to its surface. An n-type semiconductor layer having a zinc blend crystal structure is grown, a diffusion mask having a slit-like opening parallel to the [011] direction of the semiconductor layer is applied to dope the gate region, and a p-type impurity is added to the n-type semiconductor layer. anisotropically etching into the p-type doped region using the diffusion mask as an etch mask to form overhanging sides; removing the mask; and forming a contact metal for the gate in a single step by vapor deposition, defining the gate region by etching, and separating the source, drain and gate from each other.