JPS6126089B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an information processing device that performs pipeline advance control. Improving calculation methods to speed up information processing equipment,
A buffer storage system or a advance control system is adopted in which a subsequent instruction is read out prior to execution of an instruction, and furthermore, operands for the subsequent instruction are read out. A so-called pipeline control method is an advanced form of the advance control method. This method was published in the publication ``Computer System Technology'' (edited by Tatsu Motooka) published by Ohmsha on April 20, 1971, pages 93 to 93.
You can refer to page 105. In an information processing device that employs a pipeline control method, during instruction execution, for example, instruction fetching, instruction decoding, address calculation, buffer storage device reading, and instruction execution operations are synchronized by a clock, and the logic unit (hereinafter referred to as pipeline control stage) is performed separately at each stage. That is, when a predetermined operation is completed in a certain pipeline control stage, the operation result is sent to the subsequent control stage, and at the same time, input information regarding the next instruction is received from the previous pipeline control stage. In such a pipeline control method, 1
The execution time of one basic instruction is the number of clocks from when the instruction enters the first control stage of the pipeline until it is processed by the final control stage, i.e.
It is not determined by the number of pipeline stages, but is close to the time (one clock) required to effectively pass through one pipeline control stage. When seeking to improve the performance of an information processing device using the pipeline control method described above, it is possible to reduce the performance per pipeline control stage to shorten the time required for one clock, and conversely to increase the number of pipeline control stages. You can also increase it. On the other hand, in the case of a branch instruction, “Instruction fetch → Instruction decode → Address calculation →
Accessing the buffer storage device by that address →
It is necessary to shorten the time of the branch operation itself, which consists of ``fetching the branch destination instruction.'' When a pipeline control method is adopted, the execution time of this branch instruction is

[Table] 〓Number〓
The second term clearly depends on the number of pipeline stages. In order to speed up basic arithmetic instructions, when the number of pipeline stages is increased as the clock interval is shortened, branch operations are also executed because they are synchronized with the clock that advances the pipeline control stage. As a result, the number of pipeline stages required increases and "synchronization loss" is accumulated, and the execution time of the branch operation expressed by the above-mentioned product actually becomes longer.
The "synchronization loss" mentioned here arises from the following reasons. (1) When determining the pipeline period (clock), the one with the maximum delay time is set among the pipeline control stages, and the other pipeline control stages are set according to the clock time of one cycle. You can play pointlessly. When a branch operation is executed, a plurality of pipeline control stages are used, and in the process, a pipeline control stage with such wasteful play is passed through. (2) When synchronizing with a clock, clock phase shifts may occur due to variations in component and load characteristics, etc., but when determining the clock cycle, it is necessary to allow for a margin of delay time to absorb this effect. In addition, the flip-flops that constitute the registers of each pipeline control stage basically only have the function of holding information, and the above-mentioned branch operation ("fetching an instruction →...→fetching a branch destination instruction")
Logical processing is not essential. This flip-flop setting holding delay time must be included in the maximum delay time when determining the clock cycle. That is, when passing through n pipeline control stages, n clock phase variation guarantee times and n flip-flop setting holding times are added. As described above, in the conventional pipeline control system, when the clock period is shortened in order to speed up basic instructions and the number of pipeline stages is increased accordingly, there is a drawback that the branch operation becomes slower. SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus in which the number of clocks required for branch operations that occur when the number of pipeline stages is increased to increase the speed of the information processing apparatus. The apparatus of the present invention includes an instruction decoding means for decoding an external instruction, a first buffer memory circuit, and a plurality of pipeline control stages, and when the instruction decoded by the instruction decoding means is not a branch instruction, the apparatus is provided with a main memory. operand advance control means for generating an address for accessing the address and performing a search operation in the plurality of pipeline control stages to determine whether an operand specified by the address is stored in the first buffer storage circuit; an instruction execution means connected to the pipeline control stage of the operand advance control stage to execute an instruction; and a second buffer memory circuit, and when the instruction decoded by the instruction decoding means is a branch instruction, the operand advance control Branch control means that generates an address for accessing the main memory device independently of the means and performs a search operation to determine whether a branch destination instruction specified by this address is stored in the second buffer memory circuit. When the branch destination instruction is retrieved from the second buffer storage circuit by the branch destination control means, the branch destination instruction is supplied to the instruction decoding means at a timing unrelated to the synchronization clock, and the branch destination instruction is and means for controlling the branch instruction to be held in the instruction decoding means until the branch instruction is supplied to the instruction decoding means. Next, the present invention will be explained in detail with reference to the drawings. The instruction decode stage of the present invention in FIG. 1 decodes the instruction code (OP) of the 32-bit instruction register 1, the 32-bit x 16-word index register 2, the 32-bit x 16-word base register 3, and the instruction register 1. The instruction decoder 4 includes an instruction decoder 4. The operand advance control unit 5 controls blocks 11 to
43, of which the address calculation control stage is comprised of registers 11 to 15 and a three-input first address adder 16. The buffer storage index control stage also includes registers 21, 22 and 23,
It consists of a first directory array 24, and a register 23 holds an address of a main memory (not shown) that specifies an operand. The buffer memory read control stage is composed of registers 31, 32, and 33, and the first buffer memory data section 34, and the data transfer control stage is composed of registers 41, 42, and 34.
and 43. The execution unit is composed of registers 51, 52 and 53, a 32-bit arithmetic unit 55, and an execution register (ER) 54 of 32 bits x 16 words. The branch advance control unit 6 includes a 3-input second address adder 60, a second directory array 61 of a second buffer memory circuit,
Second buffer storage data section 6 corresponding to this array
2. Has an instruction block selector 63 for comparing directories and selecting data, an instruction buffer register 64, an instruction selector 65, and a plus 1 function.
It consists of a 32-bit instruction address counter 66 and an instruction address selector 67. The instruction word in this embodiment consists of an 8-bit instruction code part (OP) and a 4-bit execution register designation part R, as shown in the instruction register 1 in FIG.
1. 4-bit index register estimation section (x2) for estimating the address of the operand on the main memory, 4-bit base register specification section B
It consists of 2.12-bit displacement D2. When an instruction is set in the instruction register 1, it is read out to the index register 2 and base register 3 by the index register designation section x2 and the base register designation section B2 of the instruction register 1, respectively. At the same time, the instruction code (OP) stored in the instruction register 1 is decoded by the instruction decoder (DCD) 4, and as a result, a non-branch related instruction (for example, the contents of the operation register R1 and the address (B2) + (X2) + D ₂₎ , the read outputs of index register 2 and base register 3 are read out from registers 14 and 1.
5 and displacement D ₂ is also sent to register 13. At this time, the execution register specification section R1 specifies the execution register (ER) 54.
A designation of the type of operation in the execution unit (for example, fixed-point addition) is created based on the decoder (DCD) 4 and stored in the register 11. The information newly specified in the registers 13, 14, and 15 of the address calculation control stage of the operand advance control unit 6, which is composed of a pipeline, is added by the first address adder 16 and becomes an address on the 32-bit main memory. is created and stored in register 23 of the next buffer storage index control stage in the pipeline.
is stored in At the same time, the contents of registers 11 and 12 are stored in registers 21 and 22. The address on the main memory stored in the register 23 becomes an input to the first directory array 24,
The address of the first buffer storage data section 34 is created and stored in the register 33 of the buffer storage read control stage. At this time, the contents of registers 21 and 22 are simultaneously stored in registers 31 and 32. In the buffer memory read control stage of the pipeline, register 33
The contents of the first buffer storage data section 34 are read with the contents of the registers 41 and 32, and the contents of the registers 31 and 32 are
At the same time, one word (32 bits) of data is stored in the register 43 of the data transfer control stage.
The data transfer control stage of the pipeline transfers combined instruction and data information from the buffer to the execution unit. When the execution unit is ready to accept the next instruction, register 4
The contents of registers 1, 42, and 43 of the execution unit are transferred to registers 51, 52, and 53. In the execution unit, the data from the execution register 54 at the address specified by the register 52 and the data stored in the register 53 are subjected to an operation (for example, fixed-point addition) specified by the register 51 in the arithmetic unit 55.
The result is returned to the execution register 54 specified by the register 52, and execution of the instruction is completed. A more detailed operation of the first buffer memory circuit consisting of a buffer memory index control stage and a buffer memory read control stage of the pipeline will be explained with reference to FIG. The first buffer memory circuit realized in FIG. 2 is a set associative type buffer memory configured to hold relatively frequently used blocks mainly among operands in the main memory. It is a circuit. The operating principle of the set associative buffer memory circuit is as follows:
MARCH, 1969 “CONCEPTS FOR BUFFER”
You can refer to "STORAGE" pages 9 to 13.
Register 23 stores a 32-bit address on main memory. This address is divided into three parts and sent to the buffer lookup stage. Bits 0-20 are called the tag number, bits 21-28 are called the set number, and bits 29-31 are called the word number. The first directory array 24 includes four address arrays 2410 to 2410.
413 and one replacement algorithm information section 2
414. Each address array holds a 21-bit tag number and 1 valid display bit, and a replacement algorithm information section 2414.
Both have memory circuits for addresses 0 to 255 addressed by bits 21 to 28 of register 23.
The first directory array 24 is 256
×4=1024 blocks of address information on the main memory can be stored. One block consists of eight words, which is the unit in which data in the main memory is allocated to the first buffer memory circuit, and is also the unit in which data is transferred from the main memory to the first buffer memory circuit. Set number of register 23 (bits 21-2
8) Address array 2 read out with 8 bits
The tag number part of the outputs 410 to 2413 and the tag number part of the register 23 (bits 0 to 2)
0) are compared by comparators 2420 to 2423,
The match output is ANDed with the valid indicating bit of each address array in AND gates 2430-2433. When the block corresponding to the address on the main memory specified by the register 23 is held in the first buffer memory circuit, one of these four outputs becomes logic "1" and the others become logic "0". This is encoded into a 2-bit address array number by the encoder 244 and stored in the register 33 together with the set number and word number in the register 23. When the outputs of gates 2430 to 2433 are all logic "0", output line 2451 of OR gate 245
becomes logic “0”, and the data block (8
(word) is not held in the first buffer memory circuit 34. In this case, one of the four address arrays is selected using the output of the replace algorithm information unit 2414 that is simultaneously read from the first directory array 24;
Register the tag number of register 23 there, set the valid display bit to logic "1", read one block of data from the corresponding main memory, and register 3.
3, bits 19-28 are written to the block.
The details of these operations are normal operations of a set associative type buffer memory circuit, and are not directly related to the essence of the present invention, so a detailed explanation will be omitted. For convenience of understanding, the information stored in the register 33 consists of a 10-bit block number consisting of a 2-bit address array number (bits 19 and 20) and an 8-bit set number (bits 21 to 28), and a word number within the block. (bits 29 to 31). In this embodiment, the first buffer storage data section 34 has 13
It has 8192 words of data accessed by the bit register 33, and when an address is given to the register 33, one word of data is transferred to the next stage register 43 when it becomes transferable. Next, returning to FIG. 1, the operation of the branch advance control unit 6 will be explained in detail. When an instruction is stored in the instruction register 1, it is decoded by an instruction decoder 4. As a result, if it is interpreted as an unconditional branch instruction (contents of base register specification section B2 + contents of index register specification section X2 + branch to the address specified by displacement D2), the contents of index register 2, base A second address adder 6 with three inputs, the contents of register 3 and displacement D2 of instruction register 1.
given to 0. The second address adder 60 has the same function as the first address adder 16, and outputs a 32-bit branch destination address on the main memory to an output line 601. In FIG. 3, the branch destination address 601 is handled by dividing the contents of the register 23 in FIG. 2 into a tag number, a set number, and a word number. The second directory array 61 has almost the same function as the first directory array 24 shown in FIGS. 1 and 2, but as shown in FIG. 27, which is one bit less, and conversely, the word number is one bit more, from bits 28 to 31, and the block size is 16 words. That is, the second directory array 61, second buffer storage data section 62, and instruction block selector 63 provide 128 sets x 4 blocks/set x 16
Word/Block Set Associa Dave Method 2nd
It constitutes a buffer memory circuit. The second buffer memory circuit stores relatively frequently used blocks of instructions on the main memory. Instruction address counter 66 in FIG.
can set the initial value when an interrupt occurs or by other means, and also has the function of inputting the branch destination address 601 while adding 1, or returning it to the input while adding 1 to its own value. have. The instruction address selector 67 selects the branch address 601 when the instruction decoder decodes the branch instruction.
When the second buffer memory circuit is accessed using the instruction address counter 66, the instruction buffer register 64, which will be described later, becomes empty and the address 661 incremented by 1 is output. Second
Instruction block selector 63 forming a buffer memory circuit
One block of 16 words accessed by the output of the instruction address selector 67 is read out from the output 631 of the instruction address selector 67. At this time, if there is no instruction block addressed by the instruction address selector 67 in the second buffer memory circuit, the output line 632 becomes logic "0" and the corresponding instruction block is read out from the main memory (not shown). and stored in the second buffer memory circuit. The 16 words of data output to the output line 631 are given to the third selector 654, and according to the designation of bits 28 to 31 of the instruction address selector 67, one word is extracted and the first selector 65 is set to 2. Instruction source 6 through
51. Output 63 of the second buffer memory circuit
1 is also applied to a 16-word instruction buffer register 64 to store the group of instructions being read at the time. When instructions are being sequentially processed, the 16 words output from the instruction buffer register 64 are given to the second selector 653, and bits 28 to 28 of the instruction address counter 66 are sent to the second selector 653.
31 is extracted, and the first selector 6
52 to the instruction supply source 651 and set in the instruction register 1. At the same time, the instruction address counter 66 is incremented by one. When bits 28 to 31 of the instruction address counter 66 all become "0" as a result of plus 1, it means that all the instructions in the instruction buffer register 64 have been processed, so the output 661 of the instruction address counter 66 is Instruction address selector 67
, the second buffer memory circuit is accessed, and the instruction buffer register 64, first, second, and third selectors 652, 653, and 654 are operated in the same manner as in the branch operation. As is clear from the above description of the branch advance control unit, for example, when an unconditional branch instruction is set in instruction register 1, the contents of index register 2 and base register 3 are read out, and the instruction displacement section D2 is read out. At the same time, it is sent to the second address adder 60 to create the address of the branch destination instruction. The address is selected as an output by the instruction address selector 67, and the second buffer memory circuit 61,
62 and 63 are accessed to read out the 16-word instruction block 631 and it is not synchronized with the clock until it is sent to the instruction register 1 via the third selector 654 and the first selector 652. That is, the logic circuit network related to the operation from when the branch instruction is set in the instruction register 1 until the branch destination instruction is output to the instruction supply source 651 is as follows when a block including the branch destination instruction exists in the second buffer memory circuit.
Consists of only combinational circuits. As described above, in the present invention, there is no synchronization at all when reading a branch destination instruction after a branch instruction is decoded at the instruction decode stage, so the system is faster than a device using a conventional pipeline control method. Faster branching operations are now possible. The present invention is not limited to the number of pipeline stages in the embodiment, and can also be applied to cases where a conversion function from a virtual memory address to a main memory address is provided. Further, although the present embodiment has been described based on the set associative method, the present invention is not limited thereto, but is obviously applicable to buffer storage methods such as the full associative method. The present invention has the advantage that a branch instruction can be executed with the shortest delay time by providing a branch advance control unit and configuring the branch destination instruction to be read without synchronizing with a clock.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 is a more detailed diagram of the first buffer memory circuit shown in FIG. 1, and FIG. 3 is a branch advance control diagram shown in FIG. 1. Figure 3 is a more detailed diagram of the unit. 1 to 3, 1...instruction register, 2...index register, 3...base register, 4...instruction decoder, 5...operand advance control unit, 6...branch advance control unit, 11, 12, 13, 14, 15, 21, 2
2, 23, 31, 32, 33, 41, 42, 4
3, 51, 52, 53...Register, 16...First address adder, 24...First directory array, 34...First buffer storage data section, 54...
Execution register, 55... Arithmetic unit, 60... Second input address adder, 61... Second directory array, 62... Second buffer storage data section, 63...
Instruction block selector, 64... Instruction buffer register, 65... Instruction selector, 66... Instruction address counter, 67... Instruction address selector, 24
10-2414...Memory element, 2420-24
30... Comparator, 2430-2433... AND gate, 244... 4 input 2 output encoder, 2
45...OR circuit, 652, 653, 654...
First, second and third selectors.

Claims (1)

[Claims] 1. Command decoding means for decoding commands from the outside;
It has a first buffer storage circuit and a plurality of pipeline control stages, and when the instruction decoded by the instruction decoding means is not a branch instruction, it generates an address for accessing the main memory, and an operand specified by this address. operand advance control means that performs a search operation to determine whether or not is stored in the first buffer storage circuit in the plurality of pipeline control stages; and a second buffer memory circuit for accessing the main memory independently of the operand advance control means when the instruction decoded by the instruction decoding means is a branch instruction. branch destination control means for generating an address and performing a search operation to determine whether or not a branch destination instruction specified by the address is stored in the second buffer memory circuit; When retrieved from the second buffer memory circuit, the branch destination instruction is supplied to the instruction decoding means at a timing unrelated to the synchronization clock, and the branch destination instruction is supplied to the instruction decoding means until the branch destination instruction is supplied to the instruction decoding means. and means for controlling the command decoding means to hold the command.