JPS61276341A - Forming method for element separating region - Google Patents

Forming method for element separating region

Info

Publication number
JPS61276341A
JPS61276341A JP11676885A JP11676885A JPS61276341A JP S61276341 A JPS61276341 A JP S61276341A JP 11676885 A JP11676885 A JP 11676885A JP 11676885 A JP11676885 A JP 11676885A JP S61276341 A JPS61276341 A JP S61276341A
Authority
JP
Japan
Prior art keywords
film
porous
polysilicon
region
polycrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11676885A
Other languages
Japanese (ja)
Inventor
Hironori Kitabayashi
北林 宥憲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP11676885A priority Critical patent/JPS61276341A/en
Publication of JPS61276341A publication Critical patent/JPS61276341A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE:To form a separating layer by selectively perforating a polysilicon formed on an Si substrate by an anodic oxidation method in a porous state, and forming an oxide film. CONSTITUTION:Polysilicon 2 and Si2N4 film 3 are superposed on a P-type Si film 1, a resist mask 4 is coated, the film 3 is opened, and <11>B<+> ions are implanted. The resist 4 is removed, the B is thermally diffused, subjected to an anodic oxidation in HF of 40-50% to alter to a porous Si 5. Then, it is altered to an SiO2 film 6 by heat treating at approx. 1,000 deg.C in O2. The expansion of the porous Si 5 after oxidation is almost zero, and there is not step difference on the surface after the film 3 is removed. Then, a laser beam is emitted to the polysilicon 2, or the polysilicon 2 is heated to 1,100-1,200 deg.C by a linear heat source, and recrystallized to form a single crystal region 10. According to the construction, an element separation of a wide region can be readily performed.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、半導体装置における素子分離の製造に際し
て、容易に広い領域の分離ができるようにした素子分離
領域の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for forming an element isolation region that allows easy isolation of a wide area when manufacturing element isolation in a semiconductor device.

(従来の技術) 従来、半導体装置における半導体素子間の分離は、選択
的に酸化膜(810,)を成長させる方法(LOCO8
@あるいはl5OPLANAR法)、溝を堀って酸化M
a(Si Os )や多結晶シリコンを埋め込む方法な
どで行なわれている。
(Prior Art) Conventionally, isolation between semiconductor elements in a semiconductor device has been achieved using a method (LOCO8) of selectively growing an oxide film (810).
@ or l5OPLANAR method), dig a groove and oxidize M
This is done by embedding a (SiOs) or polycrystalline silicon.

また、最近では、第2図に示すように、選択的なエピタ
キシアル成長技術を使った分離方法も提案されている。
Recently, as shown in FIG. 2, a separation method using selective epitaxial growth technology has also been proposed.

第2図(a)〜第2図(e)は、選択エピタキシアル成
長法を用いた素子分離形成プロセスを示した例で、まず
第2図(a)に示すように(100) Si基板上1に
、0.15〜2μmの熱酸化膜2を成長し、エツチング
によって垂直状側壁を有する素子分離パターンを形成す
る。
FIGS. 2(a) to 2(e) show an example of an element isolation formation process using selective epitaxial growth. First, as shown in FIG. 2(a), a (100) Si substrate is grown. 1, a thermal oxide film 2 of 0.15 to 2 .mu.m is grown and etched to form an element isolation pattern having vertical sidewalls.

次に、第2図(b)に示すように、約0.1μmの多結
晶シリコン(または5isN4)3を堆積し、方向性エ
ツチング技術によって熱酸化膜2の側壁に多結晶シリコ
ン(tたはSil N< ) 3を残すようにする。
Next, as shown in FIG. 2(b), polycrystalline silicon (or 5isN4) 3 with a thickness of about 0.1 μm is deposited, and polycrystalline silicon (or 5isN4) 3 is deposited on the sidewall of the thermal oxide film 2 using a directional etching technique. Sil N<) 3 should be left.

最後に、第2図(e)に示すように、周囲の熱酸化膜2
と平担になるまで露出した基板Sil上に選択的にエピ
タキシアル膜4を成長することによって、素子間の分離
した構造が得られる。
Finally, as shown in FIG. 2(e), the surrounding thermal oxide film 2
By selectively growing the epitaxial film 4 on the exposed substrate Sil until it becomes flat, a structure in which the elements are separated can be obtained.

この構造では、分離領域の寸法が熱酸化膜2の膜厚とリ
ングラフィ工程とによって決められる。
In this structure, the dimensions of the isolation region are determined by the thickness of the thermal oxide film 2 and the phosphorography process.

したがって、LOCO8法やl5OPLANAR法で見
られるような、プロセス途上でのデバイス寸法の減少が
なく、高いアスペクト比が得られる。
Therefore, there is no reduction in device dimensions during the process as seen in the LOCO8 method and the 15OPLANAR method, and a high aspect ratio can be obtained.

(発明が解決しようとする問題点) しかしながら、ウェハに対する熱酸化膜2の面積が増え
ると、エピタキシアル成長時に熱酸化膜2上にnucl
eation (核形成)が生じやすくなり、選択性が
劣化すること、また熱縁膜2の側壁近傍のエピタキシア
ルSi膜4の結晶性が悪くなることなどの問題点があっ
た。
(Problem to be Solved by the Invention) However, when the area of the thermal oxide film 2 with respect to the wafer increases, nucls are formed on the thermal oxide film 2 during epitaxial growth.
There were problems such as nucleation (nucleation) becoming more likely to occur and selectivity deteriorating, and the crystallinity of the epitaxial Si film 4 near the sidewalls of the thermal edge film 2 becoming worse.

このように、従来の素子分離形成法においては、熱酸化
膜面積が増える(すなわち分離面積が増える)と分離特
性を劣化させ、半導体装置を設計する際、分離パターン
に制約を加えることになる問題点や、結晶性が悪いため
、半導体素子の電気的特性に悪影響を与える問題点があ
った。
As described above, in the conventional device isolation formation method, an increase in the area of the thermal oxide film (that is, an increase in the isolation area) degrades the isolation characteristics, which poses a problem that imposes restrictions on the isolation pattern when designing semiconductor devices. Due to its poor crystallinity, there is a problem in that it adversely affects the electrical characteristics of semiconductor devices.

この発明はl1iJ記従来技術が持っている問題点のう
ち、分離パターンに制約がある点と半導体素子の電気的
特性に悪影響を与える点について解決した素子分離領域
の形成方法を提供するものである。
This invention provides a method for forming an element isolation region that solves the problems of the prior art mentioned above, such as restrictions on isolation patterns and adverse effects on the electrical characteristics of semiconductor elements. .

(問題点を解決するための手段) この発明は、素子分離領域の形成方法において、半導体
基板上に形成した多結晶Siを陽極化成法により選択的
に多孔質化しかつ酸化膜に変えて分離領域を形成する工
程を導入したものである。
(Means for Solving the Problems) In a method for forming an element isolation region, the present invention selectively makes polycrystalline Si formed on a semiconductor substrate porous by an anodization method and converts it into an oxide film to form an isolation region. This method introduces a process to form a .

(作用) この発明によれば、素子分離領域の形成方法に以上のよ
うな工程を導入したので、半導体基板上の分離すべき領
域の多結晶SLを陽極化成法で選択的に多孔質化して酸
素雰囲気中で熱処理し、酸化膜と゛し、分離領域を形成
する。
(Function) According to the present invention, since the above-described steps are introduced into the method for forming an element isolation region, the polycrystalline SL in the region to be isolated on the semiconductor substrate is selectively made porous by anodization. Heat treatment is performed in an oxygen atmosphere to form an oxide film and to form an isolation region.

(実施例) 以下、この発明の素子分離領域の形成方法の実施例につ
いて図面に基づき説明する。
(Example) Hereinafter, an example of the method for forming an element isolation region of the present invention will be described based on the drawings.

第1図(a)〜第1図(f)は、この発明の一実施例の
工程説明図であって、順を追って説明する。
FIGS. 1(a) to 1(f) are process explanatory diagrams of an embodiment of the present invention, and will be explained in order.

この第1図(a)〜第1図(f)において、第2図(a
)〜第2図(c)と同一部分に同一符号を付して説明す
る。
In this Fig. 1(a) to Fig. 1(f), Fig. 2(a)
) to FIG. 2(c) will be described with the same reference numerals assigned to the same parts.

まず、第1図(a)に示すように、P型Si基板(10
0)1に多結晶Si 2を0.5μm〜2.0μm堆積
し、その後窒化膜(以下5iaN+膜という)3を0.
1μm成長する。
First, as shown in FIG. 1(a), a P-type Si substrate (10
0) Polycrystalline Si 2 is deposited to a thickness of 0.5 μm to 2.0 μm on 1, and then a nitride film (hereinafter referred to as 5iaN+ film) 3 is deposited on 0.5 μm to 2.0 μm.
Grows 1 μm.

次に、第1図(b)に示すように、分離すべき領域O8
i、N4膜3を公知のホトリソ・エツチング技術によっ
て除去する。そしてSL、N4膜3を除去後、イオン注
入によってSi3N、膜3、レジスト膜4をマスクにし
てB(ポロン)を約lXl0”〜I X 1015創−
2打ち込む。
Next, as shown in FIG. 1(b), the area O8 to be separated is
i. The N4 film 3 is removed by a known photolithography and etching technique. After removing the SL and N4 films 3, B (poron) was applied by ion implantation using the Si3N, film 3, and resist film 4 as masks at approximately 1X10" to IX1015.
Enter 2.

次に、第1図(c)に示すように、レジスト膜4を除去
し、熱処理によってB(、trロン)を拡散する。
Next, as shown in FIG. 1(c), the resist film 4 is removed and B (, trron) is diffused by heat treatment.

次に、40〜50%のHF(フッ酸)中で陽極化成法に
よりBが添加された分離されるべき領域の多結晶Siを
第1図(d)に示すように多孔質Si 5にする。
Next, the polycrystalline Si in the region to be separated to which B has been added is made into porous Si 5 as shown in Fig. 1(d) by anodizing in 40 to 50% HF (hydrofluoric acid). .

その後、多孔質化された領域′を900℃〜1000℃
の温度で酸素雰囲気中で熱処理し、第1図(e)に示す
ように、酸化膜6にする。酸化後の多孔質Si5の堆積
膨張はほとんどないため、Si、N、膜3除去後の光面
段差はなく、はぼ平担化される。
After that, the porous region' was heated to 900°C to 1000°C.
A heat treatment is performed in an oxygen atmosphere at a temperature of 100 to form an oxide film 6 as shown in FIG. 1(e). Since there is almost no deposition expansion of the porous Si5 after oxidation, there is no step difference in the optical surface after the removal of Si, N, and film 3, and the surface is almost flat.

また、酸化時、SL、N、膜3直下の多結晶Si2は、
3i3N4膜3によって保護されるため酸化されること
はない。
In addition, during oxidation, SL, N, and polycrystalline Si2 directly under the film 3 are
Since it is protected by the 3i3N4 film 3, it will not be oxidized.

次に、素子を形成すべき領域の多結晶Si2に20〜1
00μm程度に細く絞ったレーザビームや電子ビームを
10〜50”/seeで走査して加熱、再結晶化あるい
はカーボンヒータに代表されるような線状の加熱源を走
査速度数ml+/、、、として、基板温度を1100〜
1200℃として再結晶化することにょシ単結晶領域1
0が得られる。
Next, 20 to 1
Heating and recrystallization are performed by scanning a laser beam or electron beam narrowly focused to about 00 μm at a speed of 10 to 50 inches/see, or by scanning a linear heating source such as a carbon heater at a scanning speed of several milliliters +/-. , the substrate temperature is 1100 ~
Single crystal region 1 to be recrystallized at 1200℃
0 is obtained.

コノとき、PffiSi基板(Zoo)1上の多結晶S
i2を再結晶化するため、この再結晶化Si (単結晶
Si)は(100)の方位をもった結晶性のよいものが
得られる。
At this time, polycrystalline S on PffiSi substrate (Zoo) 1
Since i2 is recrystallized, this recrystallized Si (single crystal Si) has good crystallinity with a (100) orientation.

分離され、単結晶化された領域にMOSFETあるいは
バイポーラ素子を形成することによ!5、MOS型ある
いはバイポーラ型の集積回路を作成することが可能にな
る。
By forming a MOSFET or bipolar element in a separated and single crystallized region! 5. It becomes possible to create MOS type or bipolar type integrated circuits.

(発明の効果) 以上詳細に説明したようにこの発明によれば、半導体基
板上の多結晶Siのうち分離すべき領域を陽極化成法に
より選択的に多孔質化し、熱処理を施して酸化膜に変え
て分離領域を形成するようにしたので、分離すべき領域
が制限されることなく、多孔質化することで容易に広い
領域の分離が可能になる。
(Effects of the Invention) As described in detail above, according to the present invention, regions of polycrystalline Si on a semiconductor substrate to be separated are selectively made porous by anodization, and heat treatment is performed to form an oxide film. Since the separation area is formed in a different manner, the area to be separated is not limited, and by making it porous, it is possible to easily separate a wide area.

また、単結晶Si上の多結晶Siを再結晶化するために
、安定した配向性と良好な結晶性が得られる。
Furthermore, since polycrystalline Si on single-crystal Si is recrystallized, stable orientation and good crystallinity can be obtained.

したがって、この領域にMOSFETあるいはバイポー
ラトランジスタを形成したとき、リーク電流が少なく、
安定した特性を得ることが期待できる。
Therefore, when a MOSFET or bipolar transistor is formed in this region, leakage current is small and
It is expected that stable characteristics will be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)ないし第1図(f)はこの発明の素子分離
領域の形成方法の一実施例の工程説明図、第2図(a)
ないし第2図(C)は従来の素子分離形成方法の工程説
明図である。 1・・・P型Si基板、2・・・多結晶Si.3・・・
513N4膜、4・・・レジスト膜、5・・・多孔質S
i、6・・・酸化膜、10・・・単結晶領域。 第1図 10沸鰭轟領上へ 二の4乙日80素+9i^田尋pt或の汗〃茂方j夫の
エネl友迦明図第1図 (a) (b) (C) 埋
1(a) to 1(f) are process explanatory diagrams of an embodiment of the method for forming an element isolation region of the present invention, and FIG. 2(a)
2C to 2C are process explanatory diagrams of a conventional element isolation forming method. 1... P-type Si substrate, 2... Polycrystalline Si. 3...
513N4 film, 4... Resist film, 5... Porous S
i, 6...Oxide film, 10...Single crystal region. Fig. 1 10 To the top of the boiling fin and roaring territory 2-4 80 elements + 9 i^ Tadahiro pt some sweat〃 Shigekata Jio's energy l friend Akira Fig. 1 (a) (b) (C) Buried

Claims (1)

【特許請求の範囲】 (a)半導体基板上に多結晶Siを堆積する工程と、(
b)この多結晶Siを陽極化成法により選択的に多孔質
Siにする工程と、 (c)この多孔質Siを酸化する工程と、 (d)残つた多結晶Siを単結晶Siにする工程と、よ
りなることを特徴とする分離領域の形成方法。
[Claims] (a) A step of depositing polycrystalline Si on a semiconductor substrate;
b) A step of selectively converting this polycrystalline Si into porous Si using an anodization method; (c) A step of oxidizing this porous Si; (d) A step of converting the remaining polycrystalline Si into single-crystal Si. A method for forming an isolation region, characterized by comprising the following steps.
JP11676885A 1985-05-31 1985-05-31 Forming method for element separating region Pending JPS61276341A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11676885A JPS61276341A (en) 1985-05-31 1985-05-31 Forming method for element separating region

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11676885A JPS61276341A (en) 1985-05-31 1985-05-31 Forming method for element separating region

Publications (1)

Publication Number Publication Date
JPS61276341A true JPS61276341A (en) 1986-12-06

Family

ID=14695248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11676885A Pending JPS61276341A (en) 1985-05-31 1985-05-31 Forming method for element separating region

Country Status (1)

Country Link
JP (1) JPS61276341A (en)

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