JPS61280169A - Image processing device - Google Patents

Abstract

PURPOSE:To realize the floating binarization of digital video signals by a simple constitution by providing a converting device that attenuates the difference from the specified central value of digital video signals, a delaying device that delays the output and a comparing device that compares the output and digital video signals and outputs binarization signals. CONSTITUTION:The peaks of digital video signals GI by black picture element are represented by P1, P2, the peak by white picture element is represented by P3 and the average levels of black picture element and white picture element are shown by g1, g2 respectively. An LUT 1 converts such digital video signals GI by equation GO1=aGI+b(1-a) and generates a conversion output GO1. In the above equation (a) is the quantity of attenuation, and (b) is the central level of the attenuation. The conversion output GO1 is inputted to a shift register 2, and shifted synchronously with a picture element clock CLK and the output GO2 delayed by (n) picture elements from GI is obtained. Then, the delayed output GO2 is compared with digital video signals GI by a comparator circuit 3. When GI<GO2 as the binarization signal output, it is judged as the black picture element, and 1 is outputted, in other cases, it is judged as the white picture element, and O is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image processing device that inputs a digital video signal and performs floating binarization.

(Prior art) Binarization processing of analog video signals has traditionally been carried out using two methods.
Change the threshold for value conversion according to changes in the brightness of the image,
A floating 2ifl method is being used.

Methods include methods that use average values within a certain range and methods that use delayed signals.

(Problems to be Solved by the Invention) However, there has been no suitable method for converting digital video signals into floating binarization. For example, Figure 3 (A
) peak Pz due to black pixels of digital video signal GI
, P2 and the peak P3 due to white pixels, only P2 is detected at a certain threshold θ, and P+ e P3
cannot be detected.

The present invention has been made to solve the above problems, and is a binary image processing method that converts a digital video signal into a floating binary image.
l! The purpose is to realize a device with a simple configuration.

(Means for Solving the Problems) The m-image processing device according to the present invention is an image processing device that inputs a digital video signal pixel by pixel and performs binarized image processing. ! !
The apparatus includes a converting means for inputting a digital video signal and converting it into a value in which the difference from a predetermined center value is attenuated, a delay means for delaying the output of the converting means by a predetermined pixel, and an output of the delay means. The present invention is characterized by comprising a comparison means for comparing the digital video signal and outputting a binarized signal.

(Function) According to the im* processing device configured as described above, the conversion means approaches the digital video signal to a predetermined center value, and the delay means delays the output by comparing the digital video signal with the threshold value. By floating the level, it is possible to perform binarization processing that corresponds to local changes.

(Example) The present invention will be explained in detail below using the drawings.

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention. 1 is for TV camera output etc.
A look-up table (hereinafter referred to as LUT) that inputs the D-converted 8-pit (256 gradation) digital video signal Gl and converts it using a predetermined calculation formula, 2 is connected to the output GO+ of this LLITl and connected to the pixel clock CLK. A delay circuit consisting of a shift register that synchronously shifts a predetermined number of pixels n; 3 is a comparison circuit to which the delayed output GO2 of the delay circuit 2 and the digital video signal GE are connected;
Outputs O.

Next, the operation of the image processing apparatus having such a configuration will be explained in detail using the time chart shown in FIG.

(A> indicates the input digital video signal Gl, P
l + P 2 indicates the peak due to black pixels of the digital video signal Gr, P3 indicates the peak due to white pixels, and Q+sQ2 indicates the average levels of black pixels and white pixels, respectively. The LLI 1 converts such a digital video signal Gr using the following formula and generates a converted output G01 (see Fig. 3 (B).
)).

GO+-paG[+b(1-a) -- (1) where a (0≦a≦1) is the amount of attenuation, and b is the center level of attenuation. FIG. 2 is a characteristic curve diagram showing the conversion relationship in LUTl. That is, gain a, offset b (
1-a), and b is the center of transformation. Here, a is the size of the noise, and b is the noise bias or gt*
Determined from G2. - The conversion output G O+ of LUTl is input to the shift register 2, and shifted in synchronization with the pixel clock CLK to obtain the output G Oz delayed by n pixels with respect to Gl (see Fig. 3).
C)). Normally, it may be about n-2.

Next, the comparison circuit 3 compares this delayed output G O2 with the digital video signal MGI, and outputs G as the 2Iti signal output 80.
If I < G O2, it is determined to be a black pixel and outputs 1; otherwise, it is determined to be a white pixel and outputs O (
Figure 3 (C) (D)). In this way, changes at the local level can finally be captured.

According to the ii image processing device having the above configuration, when using a digital video signal, the floating 2
4a processing can be realized. It is also suitable for IC implementation.

Further, since the gain and offset are set by LLI, a stable and programmable binarized image processing device can be realized.

(Effects of the Invention) As described above, according to the present invention, a binary image processing device that converts a digital video signal into floating values can be realized with a simple configuration. ′

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of an image processing apparatus according to the present invention.
IRIR block diagram, FIG. 2 is a characteristic curve diagram for explaining the operation of LLJTl, and FIG. 3 is a time chart showing an example of the operation of the apparatus shown in FIG. 1. DESCRIPTION OF SYMBOLS 1... Conversion means, 2... Delay means, 3... Comparison means, Gl... Digital video signal, b... Center value. to heco(,)Q

Claims (3)

[Claims] (1) In an image processing device that performs binarized image processing by inputting a digital video signal pixel by pixel, a conversion means that inputs the digital video signal and converts it into a value in which the difference from a predetermined center value is attenuated; , an image comprising a delay means for delaying the output of the conversion means by a predetermined pixel, and a comparison means for comparing the output of the delay means with the digital video signal and outputting a binarized signal. Processing equipment. (2) The image processing apparatus according to claim 1, wherein the conversion means is constructed from a look-up table. (3) The image processing device according to claim 1, wherein the delay circuit is constituted by a shift register.