JPS60249472A - Picture signal processing circuit of facsimile device - Google Patents

Abstract

PURPOSE:To eliminate an isolated point independently of the background level of an original and the variable density of characters or the like by determining a threshold value, which is used for decision of an isolated point eliminating circuit, on the basis of the average value of picture element level in a prescribed range around a noticed picture element. CONSTITUTION:An isolated point discriminating circuit 22 consists of three delay circuits 20, three comparing circuit 8, six D-type flip flops 9, and an AND gate circuit 10. Each comparing circuit 8 decides black or which of an inputted picture signal on the basis of the threshold value outputted from a threshold value determining circuit 19 and converts this signal to a binary signal and outputs it. The threshold value determining circuit 19 determines the threshold value on the basis of the average level of picture elements which is outputted from a picture element average value calculating circuit 3. Thus, it is possible to decide white of picture elements around the noticed picture element even if the background of the original is thick, and isolated points are detected. Further, isolated points are eliminated even if characters and pictures are thin.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal processing circuit for a facsimile machine, and more particularly to the determination of 14 values for determining the number of isolated points in a processing circuit having an isolated point removal circuit.

BACKGROUND OF THE INVENTION FIG. 1 is a block 4 showing an example of a signal processing circuit of a conventional facsimile machine. That is, an image signal obtained by optically scanning a document (digital signal of 4 pixels per pixel) is input, and a signal obtained by delaying the input signal by one line by a one-line delay circuit l, and a signal obtained by delaying the input signal by one line by a two-line delay circuit are input. The signals for a total of three lines, including the signal delayed by two lines by 2 and the human input signal, are sent to the pixel average value calculation circuits 3, 3.
The X3 pixel emphasis circuit 4 and the arc are input to the point determination circuit 12. The F111 prime mean-average calculation circuit 3 calculates the average value of the pixel signal levels of 32×3 pixels around a certain pixel of interest from both signals of the three lines described in , and supplies it to the black and white determination circuit 7. The 3×3 pixel emphasizing circuit 4 emphasizes both signals of the pixel of interest using the pixel signals of the nine surrounding pixels of the pixel of interest noted in -, outputs both signals as 4 hits, and controls the gate circuit 5 and delay circuit 6. The signal is inputted to the black and white determination circuit 7 via the black and white determination circuit 7. The delay circuit 6 uses the center pixel (J) - ■ pixel) of the 32x3 pixels whose average value was calculated by the pixel average value calculation circuit 3 and the 3x3
This is a delay circuit for matching the output timing of the image signal of the pixel of interest output from the pixel emphasis circuit 4, and the gate 1
The circuit 5 is a circuit that forces the output of the 3×3 pixel emphasis circuit 4 to be white by the isolated point determination circuit of the isolated point removal circuit j2.6 In other words, the circuit 5 and the isolated point determination circuit 12 It constitutes a point removal circuit.

The black and white determination circuit 7 determines whether the pixel of interest is black or white by comparing the level of the image signal (4 hits) of the 41st pixel manually input from the delay circuit 6 with the average level supplied from the pixel+ll value calculation circuit. 1.11, convert the signal into two parts, and output it. The black and white determination circuit 7 outputs a binary image signal from which isolated points have been removed.

The isolated point determination circuit 12 includes three comparison circuits 8 and six D
Type flip-flop 9 and an I-Kate circuit 1
0, and the comparator circuit 8 determines black and white of each manually inputted image signal (4 hits) using a fixed threshold value set in the threshold value setting circuit 11, and converts it into a binary signal and outputs it. The output of each comparison circuit 8 is input to a cascade connection circuit of two D-type flip 20 tubes 9, respectively. The binary signals of the remaining 84V4 points, excluding the output of the D-type Noritub flop corresponding to the center pixel of interest, are input to the 7-digit gate circuit 10, and the binary signals of the above 8 points are all '1'. (white), the output of the AND gate circuit 1 is l', and when the output of the AND gate circuit lO is °゛l'', the gate circuit 5 forcibly sets the image signal to white level and delays it. Output to circuit 6.

In the conventional circuit described above, for example, the background level is threshold image 1.
A dark color B that is lower than the setting value of the setting circuit 11;
The disadvantage of this method is that it can only detect isolated points. In addition, in the case of a half-tone manuscript in which characters and the like are written in thorns, there is a possibility that a portion containing significant information will be removed as an isolated point.

OBJECTS OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional drawbacks and to provide a signal processing circuit for a facsimile machine that can remove isolated points regardless of the background level of a document or the shading of characters. It is in.

Structure of the Invention The image signal processing circuit of the present invention inputs an image signal of multiple bits per pixel output by optically scanning a document, and processes the image signals of multiple pixels surrounding a certain pixel of interest to a predetermined threshold value. In an image signal processing circuit of a facsimile machine having an isolated point removal circuit that forcibly outputs the image signal of the pixel of interest as white when all the results are white, The isolated point removal circuit includes a threshold value determination circuit that determines a threshold value with reference to the average value of ``-
The method is characterized in that black and white of surrounding pixels of one pixel are determined based on the output of the threshold value determining circuit.

Embodiments of the Invention Next, the present invention will be described in detail with reference to one drawing.

FIG. 2 is a block diagram showing one embodiment of the present invention.

That is, the image signal (1
A digital signal of 4 bits per pixel) is input, and the human signal is delayed by one line by the 1-line 1TL delay circuit 1, and the signal is delayed by 2 lines by the 2-line delay circuit 2. The signals for a total of three lines are input to the pixel 11 average value meter circuit 3, 3×3 pixel emphasis circuit 4, and isolated point determination circuit 22. The pixel average value calculation circuit 3 calculates both signals of 32×3 pixels surrounding a certain pixel of interest from the image signals of 3 lines described in 4.
``Calculate the leveling bell and supply it to the black and white judgment circuit 7,
The pixel emphasizing circuit 4 emphasizes both signals of the pixel of interest using the pixel signals of the surrounding nine pixels of the L-th column pixel and outputs the signal as a 4-bit pixel signal, and outputs the signal as a 4-bit pixel signal to the delay circuit 1B.

The signal is input to the black/white determination circuit 7 via the gate circuit 5 and the delay circuit 24. The delay circuits 1 and the like are delay circuits for matching the phases of the output signal of the 3×3 pixel emphasis circuit 4 and the output of the isolated point determination circuit 22, and the delay circuit 24 is a
A delay circuit for matching the output timing of the image signal of the center pixel (pixel of interest) of the 32×3 pixels whose average value was calculated by the vote average calculation circuit 3 and the pixel of interest output from the 3×3 pixel enhancement circuit 4. be.

The gate circuit 5 is a circuit that forcibly makes the image signal of an isolated pixel white based on the isolated point determination result of the isolated point determination circuit 22. The black and white judgment circuit 7 compares the image signal of one pixel (4 hits) manually inputted from the delay circuit 24 with the pixel average value and the average level value supplied from the calculation circuit 3, and determines the target pixel. It determines black and white, converts it into a binary signal, and outputs it.The black and white determination circuit 7 determines whether isolated points have been removed?
An image signal of the value is transmitted.

The isolated point '# constant circuit 22 is composed of three delay circuits 20, a comparison circuit 8, six D-type flip-flops 9, and an anchor circuit IO. The comparison circuit 8 is
Based on the threshold values output by the threshold value determination circuit 19, the black and white of each input image signal (4 bits) is determined and converted into a binary signal and output.

The threshold value determination circuit 19 determines a threshold value based on the average level of 32×3 pixels output from the pixel average value calculation circuit 3. For example, the average level itself may be used as a threshold;
When the average level is close to white or black, it is desirable to set an appropriate threshold. However, the threshold value determination circuit 18
There is a delay time such as a time until all the signals of pixels in a predetermined range around the pixel of interest are input and the pixel average value A (calculation time of the arithmetic circuit 3) before determining and outputting the threshold value.

Delay circuit 20 includes input signal and l-line delay circuits 1.
These delay circuits delay the outputs of the two-line delay circuits 2 by the above-mentioned delay time and input them to the comparator circuit 8.

The output of each comparison circuit 8 is input to a cascade connection circuit of two D-type flip-flops 9, respectively. The binary signals of the remaining eight points excluding the central flip-flop corresponding to the pixel of interest are input to the AND gate (D circuit 10 is manually operated, and when the outputs of the above flip-flops are all l" (white), the ant gate is applied. When the output of the gate circuit IO is "l", it is determined that the pixel of interest is an isolated point.When the output of the AND gate circuit IO is "l", the output of the 3x3 pixel emphasis circuit 4 is output by the gate circuit 5. Forcibly converts the image signal delayed by the delay circuit 16 into white so that it is in phase with the output of the isolated point determination circuit 22 and outputs it to the delay circuit 24.
In this embodiment, the isolated point determination circuit 22 and the gate circuit 5 constitute the isolated point removal circuit 4tlIj&.

In this embodiment, the threshold value determination circuit 19 determines the threshold value based on the output of the pixel average value calculation circuit 3, so even when the background of the document is dark, pixels surrounding the pixel of interest can be determined to be white. This has the effect of being able to detect isolated σ points.6 In addition, it is possible to remove isolated points even when the text or pictures are pale, prevent the loss of necessary information, and binarize based on the average level. It can also be sent as an image signal.

Advantages of the Invention As described in J- above, the present invention is configured to determine the threshold value for judgment of the arc point removal circuit based on the average value of pixel levels in a predetermined range around the pixel of interest. Therefore, regardless of the shading of the background, characters, pictures, etc. of the original, isolated points can be removed, and necessary information can be prevented from being omitted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of an image signal processing circuit of a conventional facsimile machine, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, l: l line delay circuit, 2: 2 line delay circuit, 3: pixel average value calculation circuit, 4: 3×3 pixel emphasis circuit, 5: gate circuit, 6: delay circuit, 7: black and white determination circuit, 8: Comparison circuit, 9: D type flip-flop, IO
: Ant gate circuit, 11: i4 value setting circuit, 12: Isolated point judgment circuit, 1 [f, 20° 24: Delay circuit, I! ]
:v! 4-value decision circuit, 22: isolated point format) circuit with i. Applicant: 11ki Denki Co., Ltd. Agent: Patent attorney: Toshimune Sumita

Claims (1)

[Claims] When inputting multiple image signals per pixel that are output by optically scanning a document, and comparing the pixel signals of a number of pixels around a certain pixel of interest with a predetermined darkness value, all of the results are white. In an image signal processing circuit of a facsimile machine having an isolated point removal circuit that forcibly outputs both signals of the pixel of interest as white, A dual signal processing circuit for a facsimile machine, comprising a threshold value determination circuit for determining a threshold value, wherein the isolated point removal circuit (iii) determines whether pixels surrounding the pixel of interest are black or white based on the output of the threshold value determination circuit.