JPH04220746A - Bus diagnostic circuit - Google Patents

Abstract

PURPOSE:To accurately and quickly detect the abnormality of a data transmission bus and to facilitate the locating of the abnormality of a system. CONSTITUTION:In resonce to a bus abnormality diagnostic request, bus diagnostic data '0' and '1' are consecutively and selectively outputted by a selective circuit 9 and supplied to respective bit lines. The OR of the output of the respective bit lines when the bus diagnostic data '0' is supplied is taken and outputted in a bus open detection circuit 10 by an OR circuit. The NAND of the output of the respective bit lines when the bus diagnostic data '1' is supplied is taken and outputted in a bus short-circuit detection circuit 11 by a NAND circuit. The open/short-circuit state of the bus can be detected by means of the output states of these detection circuits 10 and 11.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus diagnostic circuit, and more particularly to a bus diagnostic circuit for detecting bus abnormalities in a bus structure in which a plurality of data transfer modules are connected to the same bus.

0002

2. Description of the Related Art As a structure for transferring data between a plurality of data transfer modules, a structure as shown in FIG. 4 is adopted. In n (an integer of 2 or more) data transfer modules #1 to #n connected to the bus 17,
When a hardware abnormality (failure) occurs inside each module, the parity detection circuit 6 provided inside each module is configured to detect the hardware abnormal module.

However, since there is no detection means for detecting an abnormality on the bus 17,
(including the bus driver 4 and the bus receiver 5), it is difficult to specify which module the abnormality has occurred in, and there is a possibility that all modules will be replaced as a unit.

[0004] The bus control unit 7 is a circuit for granting the right to use the bus to one of the modules, controlling bus release, etc., and receives bus use requests REQ from each module.
One bus use permit A for 1 to n according to prescribed rules
CK i (i is a predetermined integer from 1 to n) is given.

Register 2 is a register for data transfer, and register 3 is a register for data reception.

[0006] In the conventional bus configuration described above, since there is no means for detecting a bus abnormality, it is difficult to determine whether the failure is on the bus or within the module. In order to identify a fault, each module is checked one by one to identify the faulty module, and only when no abnormalities are found in any of the modules is the bus abnormality identified. Therefore, fault identification is extremely easy. It's complicated.

[0007]

[Object of the Invention] Therefore, the present invention has been made to solve the drawbacks of the conventional ones, and its purpose is to easily and quickly detect abnormalities on the bus. It is an object of the present invention to provide a bus diagnostic circuit that achieves this.

[0008]

According to the present invention, there is provided a data transfer bus, a plurality of modules that mutually transfer data via the bus, and a bus control unit that grants one of the modules the right to use the bus. A bus diagnostic circuit in a data transfer system comprising: a bus diagnostic circuit that selectively selects logic "0" and logic "1" as data for bus diagnosis in response to a bus diagnostic request, and each bit constituting the bus; and detection means for detecting the output state of each bit line of the bus when logic "0" and logic "1" are respectively supplied, and the detection result of the detection means is Accordingly, there is obtained a bus diagnostic circuit characterized in that the open and short states of the bus are detected.

[0009]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.
Portions equivalent to those in FIG. 4 are indicated by the same reference numerals. The bus diagnostic circuit according to this embodiment has a logic “0” as bus diagnostic data.
” and logic “1”, and a tri-state circuit 8 that outputs the output of the select circuit 9 onto the bus.
are provided in a number equal to the bit width of the bus 17,
Bus diagnostic data is supplied from the tri-state circuit 8 to the corresponding bus bit lines. Furthermore,
Short-circuit detection circuit 11 that detects short-circuit conditions on the bus
and an open detection circuit 10 that detects an open state.
From a diagnostic flag 14 indicating that the bus is in the diagnostic state, AND gates 12 and 13, and an inverter 15 for taking in each output of the open and short detection circuits 10 and 11 into the error display register (EIF) 16 in the bus diagnostic state. It has a timing circuit.

The open detection circuit 10 is an OR gate that receives outputs from each bit line of the bus 17, and its output is taken into the register 16 by the timing circuit 12. The short detection circuit 11 is a NAND gate that receives outputs from each bit line of the bus 17, and its output is taken into the register 16 by the timing circuit 13.

In such a configuration, from #1 module to #
If a hardware failure (20) occurs in the #1 module while data is being transferred to the #2 module, invalid data is sent onto the bus 17 and is transferred to the receive register 3 of the #2 module. Set. Therefore, since data fraud is detected by the parity detection circuit 6 of the #2 module, the #1 module can be used as a replacement unit. The above is the same as the conventional example.

Next, detection when a bus failure (21) occurs in the bus section of module #1 (including drivers/receivers 4 and 5) is as follows. Immediately after turning on the power,
Diagnostic flags (TF0, TF1
) 14 to the diagnostic state.

In order to first detect the open state of the bus, the diagnostic flag 14 is set to "10". As a result, each tristate circuit 8 is turned on, diagnostic data "0" from each selection circuit 9 is supplied to each bit line of the bus 17, and the timing circuit 12 is
5 is turned on, and the output of the open detection circuit 10 becomes ready to be taken into the register 16.

Here, if even one of the bit lines of the bus is in an open state, the bit line output of that open state (input to the OR gate 10) becomes "1", and the other normal bit line outputs become "1". All will show "0". Therefore, at this time, the OR gate 10 which is an open detection circuit
The output becomes "1", which is taken in by the timing gate 12 and set in the display register 16, and the bus open state is detected.Next, to detect the bus short state, the diagnostic flag 14 is set. Set “11”. As a result, each tri-state circuit 8 is turned on, diagnostic data "1" is supplied from the selection circuit 9 to each bit line of the bus 17, and the timing circuit 13 is turned on, so that the output of the short detection circuit 11 is turned on. register 1
6 becomes ready for import.

[0016] Here, if even one of the bit lines of the bus is in a short-circuit state, the bit line output (input to the NAND gate 11) of the short-circuit state becomes "0",
All other normal bit line outputs will show "1". Therefore, at this time, the output of the NAND gate 11, which is a short circuit detection circuit, becomes "1", which is the timing gate 1.
3 and set in the display register 16, and a bus short condition is detected.

FIG. 2 is a circuit diagram of another embodiment of the present invention, in which parts equivalent to those in FIG. 1 are designated by the same reference numerals. In the embodiment shown in FIG. 1, the bus diagnosis is performed immediately after the power is turned on, but in this embodiment, the bus diagnosis is performed between normal operations. To this end, bus open and short circuits are detected in response to the timing of generation of a bus unused signal NACK from the bus control unit 7 indicating the bus unused state.

The tri-state circuits 8 are turned on by this bus unused signal NACK, and this signal NACK is turned on by F.
Set F (flip-flop) to 30. This FF3
The inverted output of 0 and the signal NACK are connected to the timing gate 12.
The reverse phase output thereof is input to the timing gate 13 and is used as a selection signal for the selection circuit 9. The other configurations are the same as those in FIG.

When a bus failure (21) occurs, the differential circuit consisting of the FF 30 and the NAND gate 31 operates for the first 1T (clock cycle) while the bus is not in use.
As in the example of FIG. 1, diagnostic data "0" is sent onto the bus, and the open detection circuit 10 and its detection timing circuit 12 detect the bus open state. Next, at 1T, diagnostic data “1” is sent onto the bus,
A bus short state is detected by the short detection circuit 11 and its detection timing circuit 13.

FIG. 3 is a block diagram showing the bus control section 7 shown in FIGS. 1 and 2 in more detail. This bus control unit 7 receives a bus request signal REQ1 from each module #1 to #n.
A bus request holding register (REQR) that holds ~REQn.
) 40, a bus request priority circuit 41 that determines the priority of bus requests from each module #1 to #n, and bus use permission signals ACK1 to A to each module #1 to #n.
The bus use permission holding register (ACKR) holds CKn.
) 42, an OR gate 43 that outputs a bus unused signal NACK indicating that all modules #1 to #n are in a bus unused state, and inactivates bus use permission signals ACK1 to ACKn at the end of data transfer. The reset circuit 45 is composed of an OR gate. Inputs to this reset circuit 45 are data transfer end signals END1 to ENDn indicating that data transfer has been completed in each module #1 to #n.

[0021]

[Effects of the Invention] As described above, according to the present invention, by providing a bus abnormality detection circuit that detects bus open and short circuit states, abnormalities on the bus can be detected immediately, so the location of the abnormality can be identified. This can be done easily and quickly, and has the effect of shortening the recovery time when a system goes down.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

FIG. 3 is a block diagram showing a specific example of a bus control section.

FIG. 4 is a block diagram for explaining a conventional failure diagnosis method.

[Explanation of symbols]

8 Bus driver 9 Selection circuit 10 Open detection circuit 11 Short circuit detection circuit 12 Open detection timing circuit 13 Short circuit detection timing circuit 16 Abnormality display register 17 Bus

Claims (1)

[Claims] 1. A data transfer system including a bus for data transfer, a plurality of modules that mutually transfer data via the bus, and a bus control unit that grants one of the modules the right to use the bus. a bus diagnostic circuit, comprising means for selectively supplying logic "0" and logic "1" as data for bus diagnosis to each bit line constituting the bus in response to a bus diagnosis request; , detection means for detecting the output state of each bit line of the bus when logic "0" and logic "1" are respectively supplied,
Depending on the detection result of this detection means, the bus is opened or
A bus diagnostic circuit characterized by detecting a short-circuit condition.