JPS6129022B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram controlled data processing device.

In a data processing device using a microprogram control method, the control storage section in which various microprograms are stored may be a fixed storage device or a rewritable storage device.

In a data processing device equipped with a control storage section consisting of a fixed storage device and a control storage section consisting of a rewritable storage device, control is performed based on the contents (microprogram) of the latter control storage section. In cases where the control memory of the latter is generally treated as different from that of the former,
Control operations were performed only based on the contents of the latter control storage section. For this reason, there was a drawback that microprograms stored in advance in a control storage section constituted by a fixed storage device could not be used.

The present invention has been made in view of the above circumstances, and its purpose is to perform address control in common for a first control storage unit consisting of a fixed storage device and a second control storage unit consisting of a rewritable storage device. Therefore, the first control storage section and the second control storage section can be handled at the same level, and the microprogram stored in the second control storage section can also handle the first control storage section. The object of the present invention is to provide a convenient data processing device that can use the contents.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the main structure of a data processing apparatus according to the present invention, and the arithmetic control section and the like are omitted. In the figure, 1 is a main memory where user instructions and data are stored, 2 is an instruction register where user instructions read from the main memory 1 are held, and 3 is a microaddress that is input-controlled and is uniquely determined by the user instruction. It is a gate where In this embodiment, the instruction code portion of the user instruction is configured to match the microaddress.

4 is an address control unit that controls the addresses for the first control storage unit 8 and the second control storage unit 9; 5 is the output of the gate 3 and the address control unit 4;
The multiplexers 6 and 7 select one of the outputs of the multiplexer 5, that is, the address, and the corresponding first control storage section 8.
and a driver for sending data to the second control storage section 9.

8 is a first control storage section which is composed of a fixed storage device and stores various microprograms; 9;
is a second control storage section which is composed of a rewritable storage device and stores various microprograms. The first control storage section 8 and the second control storage section 9 each have different address areas.

10 is a gate that controls the output of the readout output of the second control storage section 9 to the register 11; 11 is the gate 1;
This is a microinstruction register in which the output of 0 and the readout output of the first control storage section 8 are held as necessary. 12 is a driver that sends the contents of a specific field of the microinstruction register 11 to a decoder (not shown); 13 is a multiplexer that selects either the contents of the specific field (address section) of the microinstruction register 11 or the output of the multiplexer 5; It is. The output of this multiplexer 13 is given to the address control section 4.

14 is an address register. Address register 14 holds a read/write address for second control storage section 9 when data input/output is performed between second control storage section 9 and data bus 18 . 15 is a multiplexer for selecting either the content held in the address register 14 or the output of the multiplexer 5; 16;
₁ , 16 ₂ are gates. Gate 16 ₁ , 16
₂ is connected between the data bus 18 and the second control storage section 9, and between the data bus 18 and the address register 14.
Controls data input/output to and from. 17 is a data register in which the read output of the second control storage section 9 is held, and 18 is a data bus. In this embodiment, when the second control storage section 9 is accessed by the read address held in the address register 14, the gate 10 closes and the gate ₁₆₁ opens, thereby controlling the second control storage section 9. The read output of the second control storage section 9 is sent onto the data bus 18.

FIG. 2 shows an example of a memory map of the first control storage section 8 and the second control storage section 9 according to the present invention. As is clear from the figure, the first control storage unit 8 has an address “0000” ₁₆ in hexadecimal notation.
~ “0FFF” ₁₆ is assigned, and the address “1000” ₁₆ is assigned to the second control storage unit 9 in hexadecimal notation.
“13FF” ₁₆ is assigned. In the area of addresses "1000" ₁₆ to "100F" ₁₆ of the second control storage section 9, control tables (16 types) are stored for each address.

In this embodiment, the above control table is used when a user instruction retrieved from the main memory 1 specifies a microprogram stored in the second control storage section 9 (hereinafter referred to as an extended user instruction). It has meaning. That is, each control table has a one-to-one correspondence with each of the above extended user commands. Each extended user instruction is assigned an instruction code (OP code) from “A0” ₁₆ to “AF” ₁₆ , and correspondingly, addresses “1000” ₁₆ to “100F” of the second control unit 9 are assigned. ₁₆ control tables are provided.

The control table has a control information section, a type designation section, and an entry address section. Here, the control information section indicates whether or not the corresponding command is defined, and if the command is defined,
The control information section is configured to be an instruction code indicating an unconditional branch instruction of a microinstruction.
In addition, the type specification section specifies the type of instruction (instruction type), and there are six types (RR
The type of the user instruction (SF type, SF type, RX type, RI type, SS type, SP type) is specified. In the figure, OP indicates an instruction code, R1 indicates a first operand, R2 indicates a second operand, N indicates auxiliary data, and I2 indicates second operand data. Further, L1 indicates the length of the first operand, L2 indicates the length of the second operand, L indicates auxiliary data, and D1 and D2 indicate the addresses of the first and second operands, respectively. When the bit indicated by the symbol * is "0" or "1", these become base register modification or location relative address expression.

Referring again to FIG. 2, the entry address section specifies the start address of the address area in which the microprogram of the instruction execution portion is stored.

Also, the address “1010” of the second control storage unit 9
₁₆ stores the contents of the control table corresponding to the extended user command to be executed read from the second control storage section 9, and furthermore, addresses "1011" ₁₆ to
“13FF” ₁₆ is designed to store various microprograms.

On the other hand, addresses “00A0” ₁₆ to “00AF” ₁₆ of the first control storage unit 8 contain the following information for each address:
A microinstruction for branching to a microprogram stored in a specific address area within the same first control storage 8 is stored. The microprogram is activated in response to the extended user command, and is a specific microprogram for checking the control table (hereinafter referred to as control information check program).

Next, the operation of the configuration shown in FIGS. 1 and 2 will be explained with reference to the flowchart shown in FIG. For example, assume that an extended user instruction specifying a microprogram in the second control storage section 9 has been read out from the main memory 1. This extended user instruction is held in the instruction register 2. The instruction code part data (any one of “A0” ₁₆ to “AF” ₁₆ ) of the extended user instruction held in the instruction register 2 is sent as a microaddress through the gate 3, multiplexer 5, and driver 6 in order. The signal is applied to the first control storage section 8. Similarly, the data in the instruction code section is passed through the gate 3, multiplexer 5, multiplexer 15, and driver 7 in order to the second
is given to the control storage section 9 of.

Micro address (address “00A0” ₁₆ to “00AF”) indicated in the instruction code part of the extended user instruction
₁₆ ) is the address area of the first control storage unit 8 (address “0000” ₁₆ to “0FFF”
₁₆ ). That is, the microinstruction at the corresponding address position in the first control storage section 8 is read out by the microaddress. It is clear that this microinstruction is an instruction that specifies a branch to the control information check program. This microinstruction is held in the microinstruction register 11. The contents of the field specifying the branch destination address of the microinstruction register 11 are then applied to the first control storage section 8 through the multiplexer 13, the address control section 4, the multiplexer 5, and the driver 6. As a result, the control table in the second control storage section 9 is checked by the control information check program stored in the first control storage section 8.

That is, the address of the control table corresponding to the instruction code of the extended user instruction (any one of addresses "1000" ₁₆ to "100F" ₁₆ ) is determined by the arithmetic control unit (not shown) based on the control information check program. By processing the data bus 18
and address register 1 through gate 16 ₂
4. The contents held in the address register 14 are provided to the second control storage section 9 through the multiplexer 15 and the driver 7. As a result, the contents of the corresponding control table are read out, and the readout output is held in the data register 17 through the gate 16 ₁ and the data bus 18. At this time, the gate 10 is closed and output to the microinstruction register 11 is prohibited. In this way, in this embodiment, when the contents of the second control storage section 9 are used as data, the corresponding address is given from the address register 14, and the structure is such that the read data is not output to the microinstruction register 11. has been done. This allows the control table in the second control storage section 9 to be checked by the control information check program in the first control storage section 8.

The contents of the control table held in the data register 17 are checked according to the flowchart shown in FIG. That is, first, by examining the control information field, it is checked whether a corresponding extended user command is defined (step S1). If it is not defined (in this embodiment, if at least one of the bits in the control information field is not logic "1"), the instruction is considered illegal and becomes a cause of a program check interrupt. As described above, according to this embodiment, if an attempt is made to execute an undefined user command, it can be treated as illegal, thereby making it possible to prevent malfunction of the command.

Next, if an instruction is defined by the control information section (in this embodiment, all bits of the control information section are logical "1"), the entry address section is examined (step S2). If the start address of the desired microprogram indicated in the entry address section is not in the address area of the second control storage section 9, the corresponding instruction is deemed to be illegal.

On the other hand, if the contents of the entry address field are correct, the type designation field is checked (step S3). If a type other than the six instruction types shown in FIG. 3 is specified, the instruction becomes illegal. After the above-described control table check (steps S1 to S3) is performed, an operand fetch is performed if the instruction requires an operand fetch. (Step S4). On the other hand, the contents of the corresponding control table are copied to address "1010" ₁₆ in the second control storage section 9.

That is, by holding a specific address (address “1010” ₁₆ ) in the address register 14, the contents of the control table held in the data register 17 are changed to the data bus 18, the gate 1
₆₂ to the address location designated by the address register 14 of the second control storage section 9 (address "1010" ₁₆ ).

After checking the control table (and after an operand fetch, if necessary), the control information check program branches to address "1010" ₁₆ . That is, the contents of the address portion of the microinstruction specifying the branch address "1010" ₁₆ are given to the address control unit 4 through the microinstruction register 11 and multiplexer 13. The address control section 4 supplies the contents of the address section of the microinstruction to the first and second control storage sections 8 and 9, respectively.

In this example, address “1010” ₁₆ is the second
Therefore, control is transferred to the second control storage section 9. As a result, the address “1010” in the second control storage unit 9
The contents of ₁₆ are read. On the other hand, when control is transferred to the second control storage section 9, the gate 10 performs an opening operation. As a result, the readout output of the second control storage section 9, that is, the contents of the control table are as follows:
It is held in the microinstruction register 11 through the gate 10.

The control information section, which is a component of the control table, also serves as the instruction code for microinstructions.
When an instruction is defined as in this embodiment, the control information section specifies an unconditional branch instruction. At this time, the microinstruction register 11
The contents of the predetermined fields, that is, the contents of the entry address section of the control table, are the multiplexer 13, address control unit 4, multiplexer 5, multiplexer 15, and is applied to the second control storage section 9 through the driver 7. As a result, a branch is made to a predetermined microprogram, and the processing of the microprogram is executed. As described above, according to this embodiment, (1) since a control table (control information section) is provided in the second control storage section 9, an undefined instruction can be executed by checking this table; It is possible to treat the command as illegal, thereby preventing malfunction of the command.

(2) Since the control table is provided with a type designation section for designating the command type, user commands (extended user commands) using the second control storage section 9 can be given flexibility.

(3) When an instruction is defined, the control information section is configured to be an instruction code indicating an unconditional branch instruction of the microinstruction, so the control information stored in the first control storage section 8 The check program simply stores the control table to be checked at a specific address (address "1010" ₁₆ ) in the second control storage section 9, and branches to that specific address after completing the check. You can branch to the specified address. In other words, since it is possible to branch to individual entry addresses (16 types in this embodiment) using a common control information check program, a dedicated control information check program (routine for branching) is required for each control table. It is convenient because there is no need to provide a , and the area of the first control storage section 8 can be used effectively.

Effects such as this can be achieved.

Further, in this embodiment, different address areas are assigned to the first and second control storage units 8 and 9, and an address control unit 4 is provided that commonly controls the control storage units 8 and 9. , as described above, the first and second control storage units 8, 9
There is no need for the microprogram to be aware of which address the address is for. For this reason, for example, the second
from the microprogram in the control storage section 9 of
Even when branching to the microprogram in the control storage unit 8 of the first control storage unit 8 and branching again to the second control storage unit 9, the first and second control storage units 8 and 9
There is no need to distinguish between the two, and it can be handled only by the difference in addresses. That is, according to this embodiment, the second control storage section 9 is treated as an extension of the first control storage section 8 and can be handled at the same level as the first control storage section 8, so that the first control storage section 9 is Storage section 8
It is convenient to be able to use microprograms (subroutines, etc.) stored in the microprogram, and the area of the second control storage section 9 can be used effectively.

The data processing device of the present invention can be applied not only to computers but also to microprogram-controlled electronic equipment whose control storage unit includes a fixed storage device and a rewritable storage device.

As detailed above, according to the present invention, it is possible to handle the first control storage section made of a fixed storage device and the second control storage section made of a rewritable storage device at the same level, and the second control storage section made of a rewritable storage device can be handled at the same level. A convenient data processing device can be provided in which the contents of the first control storage section can also be used by a microprogram stored in the control storage section of the first control storage section.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a block diagram of main parts of a data processing device, FIG. 2 is a memory map of a control storage unit according to the present invention, and FIG. 3 is a diagram showing user commands according to the present invention. FIG. 4 is a flowchart for explaining the operation. 1... Main memory, 3, 10, 16 ₁ , 16 ₂ ...
...Gate, 4...Address control section, 5, 13, 1
5... Multiplexer, 8... First control storage section, 9... Second control storage section, 11... Microinstruction register, 14... Address register, 17
...Data register.

Claims (1)

[Scope of Claims] 1. A first control storage section which is a fixed storage device and stores various microprograms and control information check programs, and a rewritable control storage section which has an address area different from that of the first control storage section. a second control storage section which is a storage device and stores a control table including control information indicating whether various microprograms and user instructions are defined and an entry address indicating the start address of the microprogram; an address control section that commonly performs address control for the first and second control storage sections; a microinstruction register that holds the readout outputs of the first and second control storage sections; An address register that specifies the address of the second control storage unit, and data that holds the control information and entry address read from the control table of the second control storage unit specified by the address register. register, and when a user instruction specifies a microprogram stored in the second control storage section, the control information check program is read from the first control storage section in accordance with the user instruction. The content of the control table read into the data register is judged by the control table, and if the content is normal, the content is branched to the entry address indicated in the control table, and if it is not normal, it is treated as illegal. data processing equipment. 2. The data processing device according to claim 1, wherein the control information section of the control table is an instruction code indicating an unconditional branch instruction of a microinstruction. 3. The control information check program includes a microinstruction that writes the contents of the control table to a specific address in the second control storage section when the control table is determined to be normal. A data processing device according to claim 2, characterized in that: 4. The data processing apparatus according to claim 3, wherein the control table includes a type designation section that designates the instruction type of the corresponding user command.