JPS6129064B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a so-called random access method for a video disc player.

Conventionally, a disk has a spiral groove with an arcuate cross section, and information relating to video and audio is recorded as a series of struts on the bottom of the groove. And, in the track (groove of one circumference) of this disk,
Information such as the track address is recorded for each track, and is mainly used by the disk supplier for quality control of the disk itself.

When such a video disk is rotating, the information being recorded is captured by a stylus sliding through the grooves, capturing changes in the relief pattern as capacitance changes or pressure changes, and thus electrically changing signals. It is read as .

Now, when playing a disc, the operation of the needle (pickup) is realized by pressing the operation button of the conventional video disc player operation system, which is electrically and mechanically systemized. When playing,
When there is a scene you want to play, press FF (fast forward) or
The needle must be moved to that position using FR (fast return) operation. For example, if you move the needle by eye, then lower it and play the scene, if it is not the desired scene, you have no choice but to raise and lower the needle many times and repeat FF or FR until the desired position is reached. This is of course the same even if the contents recorded on the disk are associated with a track address in advance, and it is not possible to cue up quickly.

In general, this type of video disk has a small track pitch of several μm, making it difficult to search for the desired track as described above.In addition, it is difficult to search for the desired track as described above. This difficulty is exacerbated by track deviations and the like during recording on the disc.

Also, for this reason, a system has been proposed that uses a type of mechanical marker display that works in conjunction with the needle as a means for indicating the position of the needle on the disk. According to this method, although the approximate position of the needle can be determined, the exact track position cannot be determined, which is still inconvenient for searching for reproduction of a desired scene.

Therefore, an object of the present invention is to provide a head access method useful for improving the above-mentioned problems.

An embodiment of the present invention will be described below with reference to the drawings.

Random access of the video disc in the present invention is realized by using information such as track addresses recorded in advance on the tracks of the disc.

Generally, video information is recorded in the form of a composite video signal that is FM modulated, and several frames are recorded on one track. For example, it is recorded as 1 frame (2 feeds) or 4 frames (8 feeds).

The information such as the track address is stored in one horizontal period of the horizontal synchronization pulse at the trailing edge of the vertical synchronization pulse, for example, 20H, as shown in FIG.
(20th horizontal period), FM
recorded in a modulated form. Note that this recording position does not necessarily have to be the 20th H.

The content of this track address and other information consists of 23 bits, for example, as shown in Fig. 2. The first bit is a start word and is of a particularly high level, that is, "1", and the second to fourth bits are an angle word. The 5th to 18th bits are address words and indicate the track address, and the 19th to 23rd bits are error bit check words and are used to check bit errors. Here, the bit width of 1 bit is approximately 2 μs, and 23 bits is approximately 46 μs, so the horizontal period (63.5 μs)
This will account for approximately 70% of the total.

A track address reading circuit for processing information such as this track address extracts and latches the 20th H information, and is constructed as shown in FIG.

In a video disc playback device (hereinafter simply referred to as a player), a disc is mounted on a turntable 1 and rotated. A needle (pickup) 2 is attached to a movement called a head and moves over the disk toward the center, and picks up the signal recorded in the groove of the disk.

This signal is reproduced by a video signal reproducing circuit 3 to become a composite video signal (NTSC system, PAL system, etc.), which is input to a 20H gate 5, and is supplied to a monitor where it is displayed. Note that such a video signal reproducing circuit is already well known and will not be described in detail here. And video signal reproducing circuit 3
A composite synchronization signal is introduced into the 20H sampling pulse generation circuit 7, and when 20H is detected, a gate flag signal C is obtained. This 20H sampling pulse generation circuit 4
The circuit consists of a vertical and horizontal synchronizing pulse separation circuit, a horizontal pulse counter, and a monostable multi-channel circuit, and will not be described in detail since it can be easily obtained with the current state of the art. A 20H gate 5 gates the composite video signal A with a gate flag signal C, and outputs a sampling signal D.

This sampling signal D is transmitted to the shift register group 10, which will be described later.
and is introduced into the clock pulse generation circuit 5'.
That is, the monostable multi-channel 6 of the clock pulse generating circuit 5' is triggered by the rising edge of the sampling signal D, and outputs a pulse E having a width sufficiently longer than that of the bit signal. The monostable multivibrator 6 has a reset terminal, and is reset when the bit signal of the sampling signal D disappears as a signal to the terminal. The clock signal generation circuit 8 is
It preferably uses X-tal oscillation such as RC, LC or Oscillation stops when the input disappears (becomes low level). here,
As mentioned above, since the width of one bit of the sampling signal D is 2 μs, the period of the clock pulse B is set to 2 μs.
The oscillation frequency is 500KHz. This clock signal generating circuit 8 receives the pulse E as a key-in input, and after the key-in input is supplied, there is a slight delay, for example, about 1 μs.
Oscillates with a delay. As a result, clock pulse B
lags behind sampling signal D.

Clock pulse B, which is the output of clock signal generating circuit 8, is introduced into shift register group 10 and used for driving it, and is also guided to base-23 counter 9. This 23-decimal counter 9 accepts input pulses as 23
That is, it rises at the rising edge of the last pulse of clock pulse B to obtain a signal G equal to the pulse width of that pulse. The monostable multivibrator 7 goes to a "low level" at the fall of the signal G and follows its own time constant, for example, it may be sufficiently long, so it may be about one horizontal period. Outputs a pulse H that continues at a low level. This pulse H is supplied as a reset signal to the monostable multivibrator 6.

In this way, the clock pulse B to be supplied to the shift register group 10 is obtained, but since the information such as the track address is 23 bits, there are 23 pulses corresponding to the number of bits, and these pulses are used for the other clock pulses. If it is a number of bits, you can change the 23-decimal counter according to the number of bits, for example.
In the case of 18 bits, it is a hexadecimal counter.

Another method for obtaining the clock pulse B is that the video signal reproducing circuit 3 has an oscillator such as a VCO used for color signal phase control and is synchronized with the reproduced signal. It is also possible to use a signal related to the oscillation output by appropriately counting down the signal. The shift register group 10 is composed of 8-bit serial-in/parallel-out shift registers 11, 12, and 13 connected in series, and reads the sampling signal D at the rising edge of the clock pulse B and inputs the shift registers 11 to 13. Shift in the direction. In this manner, when the supply of the last pulse of clock pulse B is completed, all 23 bits of sampling signal D have been completely read into shift register group 10, and are held in that state. In addition, the shift register 13
Only the most significant bit is empty.

In this shift register group 10, the contents are output from shift registers 11, 12, 13 in 8-bit parallel, and AND gates 14, 15, 16 are output.
be guided by. Note that this shift register group 10
will cause its contents to be cleared when one more input PC ₃ is supplied.

These AND gates 14, 15, 16 each consist of eight AND gates, and are formed corresponding to each bit.
6 obtains the output of the AND of the inputs PC ₂ , PC ₁ , PC ₀ and the signals input as described above. for example,
When input PC ₂ is “high level”, AND gate 14
outputs its input 8 bits independently.

The OR gate 17, into which the outputs of the AND gates 14, 15, and 16 are input, is composed of eight three-input OR gates, and the input of each OR gate corresponds to one bit each of the AND gates 14, 15, and 16. are doing. For example, the output of the second gate of each of AND gates 14, 15, and 16 is OR gate 1
7 is input to the second gate. The output of the nth gate of each of the AND gates 14, 15, and 16 is input to the nth gate of the OR gate 17. The output PB ₀ of this OR gate 17,
...PB ₇ becomes the input for the microcomputer described next. The above inputs PC ₀ , PC ₁ , PC ₂ and PC ₃ are obtained from this microcomputer.

FIG. 5 shows a block diagram of a microcomputer, and with reference to this figure, it will be referred to as a microcomputer (hereinafter referred to as a microcomputer). )
Explain the operation.

101 is a central processing unit (hereinafter referred to as CPU)
Here, decoding, control signal generation, calculations, etc. are performed. 102 is a clock generator and CPU
101 clock. In order to stabilize the clock, it is a generator using X-tal12. 103 is the system controller
It decodes control signals from the CPU 101 and generates new control signals, and also functions as a data bus buffer. A programmable peripheral interface (hereinafter referred to as PPI) 104 is a programmable interface for inputting and outputting signals to and from external equipment. A chip selector 105 selects PROM or RAM. 106 is PRCM
(progam-mable read-only memory) where system programs are stored in memory. This is read-only. Also, 107 is RAM (random
It is used for data memory (access memory) and can be written to and read from. These PPOMs
The capacity (number) of RAM 106 and RAM 107 is determined as necessary. Reference numeral 108 designates a keyboard, through which track addresses and start commands are input using push buttons. 109 is a temporary memory for data to be displayed by a data latch. A display circuit 110 is mainly a data signal drive circuit. Reference numeral 111 indicates a track address and is composed of an LED, a gas discharge tube, or the like.

Next, to explain the signal lines, 113 is called an address bus, and it is composed of 16 signal lines (16 bits), consisting of AB ₀ to AB ₁₅ 2 ¹⁶
= 65,536 addresses can be specified. usually
An address is output from the CPU 101 and sent to the PROM 106 and RAM 10 via this address bus 113.
7 addressing is performed. In this example
The lower 8 bits of AB ₀ to AB ₁₅ are PROM106,
The upper 8 bits are input to the RAM 107 and are input to the chip select 105.

114 is the line of the PROM 106 (the bar above the character in chip select means active low). What is this signal?
Decide whether to select PROM 106. Also, 11
5 is the same as 114, RAM106 ₁ (chip
enable) and selects the RAM 107.

The signal line 116 is a data bus consisting of eight lines (8 bits) DB ₀ to DB ₇ and is used for transmitting data signals. Data is input/output from D ₀ to D ₇ of the CPU 101, and then enters the system controller 103 and is powered up. This is because when several TTL devices are connected to the data bus terminal, the output from the CPU 101 does not have the ability to drive them, so the drive ability is strengthened in this way. Fifth
The data bus arrows shown in the figure indicate the direction of data transmission, and there are two types: one-way and two-way.

Signal line 117 is output from (memory read) of system controller 3, and is output from RAM1
It is input to OD (out put disable) of 07. When this signal is output (LOW), the RAM 107
It enters a read state. On the other hand, the signal line 118 is output from the system controller 3 (memory write) and input to the R/W of the RAM 107. This signal is output (LOW)
When this happens, the RAM 107 enters a write state. That is, by these two signals, REM107
Control is performed to read data from or write data to the RAM 107.

PPI104 PB ₀ ~ PB ₇ , PC ₀ ~ _{PC 7} , PA ₀ ~ _{PA 7}
A signal line 119 connected to is used for transmitting signals with external devices. Each of these consists of 8 lines (8 bits). And PB ₀ ~
Whether ports such as PB ₇ , PC ₀ to PC ₇ , and PA ₀ to _{PA 7} are used as input or output can be controlled by a program. In this embodiment, PB ₀ to PB ₇ and PA ₀ to _{PA 7} are used as input ports, and PC ₀ to _{PC 7} are used as output ports. The output of OR gate 17 in Fig. 3 is PB ₀ ~PB ₇
PC ₀ , PC ₁ , PC ₂ among PC ₀ to _{PC 7}
PC ₃ is output to the terminal shown in the same figure. Also this CB ₀ ~
PC ₇ also has input on the keyboard. Which key has been pressed can be determined by the signals input to PA ₀ to _{PA 7} .

Next, FIG. 6 shows the head operating mechanism of the disc player. 4 plungers 210, 21
Reference numerals 1, 212, and 213 drive the head and raise and lower the needle (pickup). Reference numeral 210 is a reverse solenoid, and when this solenoid operates, the head moves backward (in the direction opposite to the center of the disk) and moves rapidly. Reference numeral 211 is a forward solenoid for fast forwarding (toward the center of the disk). Reference numeral 212 denotes a play solenoid, and when this operates, the head enters play operation. 2
Reference numeral 13 denotes a pick-up solenoid which, when operated, lowers the pick-up and brings it into contact with the groove of the disk.

Next, a switch (hereinafter abbreviated as SW) 203
The power switch is a double switch. When this is turned on, the motor 224 controls the rotation of the disk, etc.
operates, and the power supply circuit of the player is turned on by the power transformer 223. 202 is a reset switch installed at the return stop position of the head (the outermost end of the head travel line) and is turned off when the head is in this position. 209 is limit switch when the head reaches the innermost edge of the disk
It becomes ON. That is, it turns ON when the performance ends and turns OFF when the head leaves this position. These 202 and 209 SWs are, for example, micro SWs.
It is a built-in type that is not attached to the front panel.

204 is a forward fast forward SW, and as long as this is pressed and turned ON, the head will perform FF operation. 2
05 is the reverse fast forward SW, which is pressed and turned ON.
While it is turning, the head moves backwards in fast forward motion. 20
6 is the play SW, and if this is pressed even momentarily and turns ON, the head will enter play operation. The play motion refers to the movement in which the needle descends onto the disk and moves along the groove of the disk at a certain speed. 207
is the pause switch and while this is pressed to the OFF side, the hand will rise from the disk surface and the head will remain at that position. Therefore, the image is not reproduced.
208 is a stop switch, and if it is turned on even momentarily, the performance will stop and the head will return. These SW203, 204, 205, 206, 20
7,208 is installed on the front panel of the player. This operation system receives signals from the microcontroller from PC ₄ ,
FF from PC ₅ , PC ₆ to terminals 225, 226, 227
Each of the input, pause input, and FR input is input as a control signal.

The operation of this operating system will be explained.

Now, if power SW203 is turned on,
The motor 224 rotates and the power transformer 223
The power supply circuit is turned on via the .

Next, when the play SW206 is pressed, the DC voltage DC
is play SW206, forward fast forward SW204 on the OFF side, land SW229 on the OFF side
(This SW is a built-in micro-SW that is ON when the head is above the disk.) is applied to the base of transistor 216, and transistor 216 is turned on. When this is turned on, the forward solenoid is activated, resulting in F, F operation (forward fast-forward operation). At the same time, capacitor 215
is charged through resistor 214 and plays SW206
It works to keep the transistor 206 on for a sufficiently long time even if it becomes OFF. Furthermore, the forward solenoid 211 moves the head in the forward direction in FF operation, turning on the reset SW 202 and keeping the transistor 216 on. Note that at this time, the limit SW 209 is on the OFF side. In this way, turning ON the play SW 206 only for a moment is sufficient.

When the FF operation continues and the head reaches the disk, the land SW 229 is turned on. Therefore, the transistor 216 is turned off and the FF operation is canceled. Then, a DC voltage DC is applied from the ON side of land SW229 to pause SW207 and transistor 2.
21, the transistor 217 is turned on, and therefore the play solenoid 212 is operated to switch to the play operation. Note that the transistor 221 is 22
When a negative pulse is input from PC ₅ as a PAUSE signal from the microcomputer to PC 6, it is turned off, and normally it is turned on.

In this way, the play operation is executed, and the information obtained from the groove of the disc through the needle is displayed on the monitor.

When you press stop SW208 and turn it on,
Since the SCR220 is triggered and turns on, the OFF side of the forward fast forward SW204 and the play SW2
Reverse solenoid 21 through the OFF side of 06
A large current is supplied to land SW2, and therefore a voltage drop occurs due to the reverse solenoid 210.
29 to the base of transistor 217, turning off transistor 217 and turning off play solenoid 212 and pick-up solenoid 213. As a result, the play operation is canceled and the head picks up and moves backward. (FR operation) In addition, stop SW20
There is no need to keep pressing it just by pressing it momentarily to the ON side of 8.

Also, when the pause SW 207 is pressed to the OFF side during the above play operation, the transistor 217 is turned off, so the play operation stops, and the head stops with the pickup raised (PAUSE operation). Continues while pressed.

Also, when the reverse fast-forward SW 205 is pressed and turned ON, only the reverse solenoid 210 works, and the other solenoids do not work because the transistors 216 and 217 are off, so the head is reversed while the reverse fast-forward switch 205 is pressed. Advance (FR operation).

Also, forward fast forward SW204 is pressed and turned ON.
When this button is pressed, the transistor 216 is turned on and only the forward fast-forward solenoid 211 operates, resulting in FF operation.

The limit SW 209 turns ON when the head reaches the end position of the disk (innermost circumference side), and turns OFF when the head deviates from this position, so as soon as the head reaches the end position of the disk, the limit SW 209 turns ON.
Therefore, the transistors 216 and 217 are turned off, and the SCR 220 is triggered via the forward fast forward SW 204 on the OFF side through the capacitor 225, and the DC voltage DC is applied to the reverse solenoid 210,
OFF side of forward fast forward SW204, play
Since the power is supplied to the SCR 220 through the OFF side of the SW 206, the reverse solenoid 210 operates to turn on the SCR 220, causing the head to move backward. When the head moves backward, limit SW209 immediately returns to the OFF side.

If the power switch 203 turns OFF during a performance, DC voltage DC is supplied from the OFF side of the power switch 203 to trigger the SCR 220, so that the head does not get stuck in the middle of the disk and stop. Similarly, the reverse solenoid 210 operates when the SCR 220 is turned on. This is because the reset SW 202 is turned OFF only when the head moves backwards and returns to the standby position.
Since it is on the ON side, the reset SW 202 is ON.
Power is supplied to the motor 224 and transformer 223 through the side, and the DC voltage DC is reset.
By being supplied to the SCR 220 via the reverse solenoid 210 through the SW 202. When the head moves backwards and returns to the standby position, the reset SW 202 is turned to the OFF side and all power is turned off.

FIG. 7 shows a schematic diagram of the mechanism of the head operating system.

The rotational force of the shaft 301 of the motor 224 is transmitted to the shaft 302 via the worm gear, and further to the gear 30.
3 to the belt 304 and then to the belt 306 via the pulley 305, and the speed of the belt 306 is made faster than that of the belt 304.
Pedestal 30 on which a head (not shown) is mounted
7 is provided with a forward solenoid 211 and a reverse solenoid 210 corresponding to the belt 306 and a play solenoid 212 corresponding to the belt 304. Therefore, when the forward solenoid 211, the reverse solenoid 210, or the play solenoid 212 is operated, the base 307 and thus the head perform forward fast forwarding, reverse fast forwarding, or play forwarding in response to the movement of belt 306 or 304.

Next, the head access operation of the above embodiment will be explained in the eighth example.
This will be explained according to the flowchart shown in the figure.

First, in step 1, input/output declarations of peripheral devices, for example input/output terminals of the PPI 104 in FIG. 5, are declared, and information can be exchanged using these input/output terminals.

Then, proceed to step 2, and set P.ADR (preset track address) and S.ADR (search address) to 0 (zero). Here, PADR means an address that the user sets in advance according to his/her wishes.
S.ADR means the address actually read from the disk by pick-up, and such PADR and S.ADR have not yet been set or read in advance, and are cleared to 0. Note that when a track on the disk is selected (preset) using the keyboard 108 and the head reaches that track, a pick-up moves down onto the disk, picks up the address of that track (search track), and displays it on the display 11. The preset PADR is also displayed on the display 11, as will be described later, and the display 11 is divided into two sections: one for PADR and one for SADR. Therefore, when no button on the keyboard 108 is pressed at first, it is necessary to display 0.
Data areas of the RAM 107 are allocated to PADR and SADR, and 0 is stored there in step 2.

Next, in step 3, PADR and SADR stored in the RAM 107 are read out, entered into the data latch 109 via the data bus, and displayed on the display 111 via the display circuit 110. This display data is stored in the data latch 109 until new data arrives.

In step 4, by operating the keyboard 108,
Performs an input judgment as to whether the information input to the PPI 104 is a PADR and start key input,
If PADR and start key are input, the process advances to the next step 5. Note that in step 4, it is impossible to exit until the keyboard 108 is pressed, PADR is selected, and the start key is input.
Of course, PADR is stored in a predetermined area of RAM 107. In step 5, PADR is read out and displayed on the display 111 via the data latch 109 and the display circuit 110. That is, the display 111
The display changes from 0 PADR to the preset value.

Next, proceed to step 6 and send the FF signal to PPI104.
Output from PC ₄ . This FF signal is input to the FF input terminal 225 in FIG. 6 via PC ₄ ,
Therefore, it enters FF operation. This FF signal is output until the head reaches the first track position on the disk, during which time the head is sent in FF operation.

The period during which this FF signal is output is as follows in step 7.
It can be determined by That is, such a period includes a position detecting means for detecting whether the head pick-up has reached the first track position of the disk, and a time period required for starting the FF operation to reach the first track position of the disk. This can be determined depending on the time detection means used for detection. Therefore, step 7 is a control to wait for the elapse of such a period.

Next, in step 8, PADR is read to determine whether it is 0 or not, that is, whether the preset track address is 0 or not.

If the result of this determination is YES, that is, PADR is 0, the output of the FF signal is stopped in the next step 11.

If the result of the judgment is NO, that is, if PADR is not 0, then in the next step 10, PADR is decremented, that is, 1 is subtracted from PADR, and then one track is skipped by FF operation according to the next step 9. Wait for a while and then return to step 8. if
If PADR is 100, the process moves to step 11 after repeating the series of steps 8, 10, and 9 100 times. That is, it waits for the head to advance by 100 tracks.

When the output of the FF signal is stopped in step 11, the process moves to the next step 12. That is, in Figure 6
Since there is no FF signal to the FF input terminal 225, the transistor 216 turns OFF and the FF operation stops.However, since the land switch 229 is on the ON side, the transistor 217 is turned ON, the play operation starts, and the pick-up drops to the disk.

In step 13, the information recorded on the disk track detected from the pickup is
OR gate 17 in Figure 3 according to PC ₀ , PC ₁ , PC ₂
is read from PB ₀ to PB ₇ as the output. Note that S.ADR of this information is stored in a predetermined area of the RAM 107.

This information is displayed on the display 111 through the delay 109 and the display circuit 110 in accordance with step 14. After this, shift register group 10 is cleared according to PC ₃ (step 15), and PPI 10 is cleared (step 15).
A PAUSE signal is output to PC ₅ of PC 4 (step 16), and the next PAUSE operation begins.

2 where the PAUSE signal is the PAUSE input terminal in Figure 6.
26, the transistor 221
OFF, the play operation stops, the pick-up is raised, information is no longer input from the disk, and the head is stopped above the disk.

In this way, the SADR obtained is generally
Not equal to PADR. This is because even if the FF operation time is set correctly in step 7, errors may occur due to disk misalignment, disk track deviation, etc. It has been experimentally confirmed that such an error is within 50 tracks.

Therefore, these points can be further improved as follows.

In this PAUSE state, follow track 18,
Perform PADR and SADR difference detection. if,
When PADR is greater than or equal to SADR, that is, when the pick-up falls before the preset track address or matches, it is necessary to proceed with the pick-up and the next step 19 is performed.
Output the FF signal on PC ₄ according to the following.

Immediately after this step, step 20 is entered to determine whether PADR=SADR.

If the result of this determination is YES, that is, PADR=SADR, the output of the FF signal is immediately stopped at step 21.

If NO, that is, PADR>SADR, in the next step 23, PADR is decremented, that is, 1 is subtracted from PADR, and then in the next step 22
Accordingly, the CPU waits for one track jump time due to the FF operation, and then returns to step 20. In this way, the difference between PADR and SADR is detected to determine the distance to which the pick-up should proceed in FF operation.
For example, if the PADR is 1000 and the SADR is 990, the difference in distance is 10 tracks by repeating such a loop 10 times and proceeding with the pick-up by the corresponding time FF operation. In this way, if you proceed with the pick-up for 10 tracks,
If the result of the determination in step 20 is YES, the process proceeds to the next step 21, where the FF signal is stopped, the FF operation is stopped, and the process proceeds to the next step 29.

If the judgment result in step 18 above is NO, PADF
<SADR, and when the pick-up has gone beyond the initially preset position, the process moves to step 24, and the FR signal is output from PC ₆ of the PPI 104. This FR signal is input to the FR input terminal 227 in FIG. 6, transistor 222 becomes conductive, and since land switch 229 is on the ON side, FR operation is started.

After this FR operation, immediately follow step 25.
It is determined whether PADR=SADR or not, and the determination result is
If it is ON, the SADR is decremented in step 26, and after waiting for the time to skip one track by FR operation, the loop returning to step 25 is repeated, and when the judgment result becomes YES, the next step 28 is executed. Therefore, the output of the FR signal is stopped, the FR operation is stopped, and the process moves to the next step 29.

Here, match PADR and SADR in step 25.
Or, if it is judged as 20, it is considered that the pick-up deviates from the matching track. Since the FR signal or FF signal is output in step 24 or 19 of the process, the pickup will continue to move until the decision is made in step 25 or 20. However, the time required for step 28 or 21 to output the FR signal or FF signal, execute the next determination step 25 or 20, and stop it is several μs.
Furthermore, even if the pickup movement signals, ie, FR signals and FF signals, are output, there are electrical and mechanical delays. When a match occurs for these reasons, it can be assumed that the pick-up is on the matching track.

When the PAUSE signal is stopped in step 29, transistors 221 and 217 are turned on, and a play operation, which is the next step 30, begins.

After entering this play operation, step 13,
Similar to steps 14 and 15, steps 31, 32, and 33 sequentially execute SADR reading, displaying it on the display 111, and clearing the shift register group 10.

After that, it enters step 34 and waits for a while, for example 5 seconds, and then enters step 2.
Clear PADR and SADR to 1.

Note that step 34 is designed so that the display of PADR and SADR is not erased immediately, but after waiting for a while.

After this, according to step 4, the keyboard 108
If there is no PADR selection or start input from , the performance ends or the stop switch 208 is activated during the performance.
When pressed, limit switch 229 or stop switch 208 causes the pickup to move away from the disk and the head to move backwards back to standby, ie, to the outermost end of the head travel line.

After that, by operating the keyboard 108 again,
When PADR is set and the start button is pressed, the head starts moving toward the preset track address PADR in the same way as above.

In the head access method of the video playback device of the present invention, as described above, the head is cued up to a track address preset by the user, so it is not possible to cue up a desired track address as in the conventional method. can solve complicated operations.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram illustrating information on the vertical retrace period of a video signal recorded on a recording medium.
The figures each show an explanatory diagram for explaining the bit arrangement of the track address in the same as above, and FIG.
Fig. 4 is a waveform diagram of each part explaining the operation of the above, Fig. 5 is a control circuit diagram for signal processing of the above, Fig. 6 is a circuit diagram of the head operation system, and Fig. 7 is a head operation system diagram. A mechanical diagram of the system is shown, and FIG. 8 is a flowchart explaining the operation of the control circuit. 3: Video signal regeneration circuit, 5: 20H gate, 1
0: Shift register group, 17: OR gate, 10
1: Central processing unit, 103: System controller, 104: PPI, 107: PAM, 108: Keyboard, 111: Display, 116: ROM, 20
3: Power switch, 210: Reverse solenoid, 211: Forward solenoid, 212:
Play solenoid, 213: Pick up solenoid.

Claims (1)

[Claims] 1. A pickup for reading signals is moved along the grooves from a disk-shaped recording medium in which video signals and audio signals are recorded in spiral grooves, and the recorded signals are read out by changes in capacitance, pressure, etc. In a video reproducing device that obtains a reproduced image and a reproduced sound, a track address at which a desired track address is desired to be cued is preset by a head access operation, and a fast-forward device of the pick-up is operated for a time corresponding to the preset track address. Move the pick-up to a track position obtained in relation to the preset track address, and respond to a comparison between the track address read from the recording medium by the pick-up and the preset track address at this track position. 1. A head access method in a video playback device, characterized in that the movement of a pickup is controlled again by