JPS6129169B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a transversal digital filter that does not use a multiplier. A conventional digital filter consists of a delay element, an adder, and a multiplier, and the tap output from each delay element is given a predetermined weight by the multiplier and added by the adder. This required a large number of multipliers, which greatly affected speed. For example _, a conventional acyclic transversal digital filter has delay elements D ₁ to _{D K-1 connected} in cascade as shown in FIG. Multipliers B ₁ to B _K are connected to the delay element D _K-1 in the middle and final stage, respectively, and the outputs of all multipliers B ₁ to B _K are added by an adder AD and output from the output terminal OUT. be. The characteristic equation of such a digital filter is as follows, assuming that the coefficient of the filter is α _i . It is expressed as However, as mentioned above, conventional digital filters require a large number of multipliers, making the circuit configuration complicated, and the coefficients of the filter are all expressed using several to several tens of different bits. However, the circuit configuration becomes more complex, and higher processing speeds are required. The present invention has been made to improve the above-mentioned conventional drawbacks, and its purpose is to provide a digital filter that can provide desired attenuation characteristics without using a multiplier. Examples will be described in detail below. FIG. 2 is a block diagram of the basic configuration of the embodiment of the present invention, where the input terminal IN, delay elements _D1 to _DK-1 , and final stage delay element _DK-1 are directly connected to the adder AD. has been done. Delay elements D ₁ to _{D K-1} are each 1
It has a word delay delay time τ, and the number of delay elements K−
The frequency characteristic F _K (ω) in the case of 1 is It is expressed as The present invention consists of arithmetic circuits having the above-mentioned basic configuration connected in cascade, and as shown in FIG. 3, F _N (ω), F _N+1 ( _ω ), . Cascade the basic configuration of characteristics. Such a cascade connection produces a multiplication effect, and a digital filter with a single peak characteristic can be constructed without using a multiplier. The characteristics of such a configuration can be expressed as follows. FIG. 4 shows a block diagram of an embodiment of the present invention, in which D ₁₁ to D ₆₇ are delay elements and AD ₁ to _{AD 6} are adders. In this embodiment, the number of delay elements of the basic arithmetic circuits is different, and six arithmetic circuits are connected in series. The frequency characteristics when any of input terminals a to c is selected are shown in Fig. 5. When input terminal a is selected, the dotted line, when input terminal b is selected, the solid line,
When input terminal c is selected, the characteristics shown by the chain line are obtained. As is clear from this characteristic curve diagram, the sidelobe level can be reduced by increasing the number of cascaded arithmetic circuits in a digital filter in which sequentially increasing numbers of delay elements constituting the arithmetic circuits are connected in cascade. It is possible to gradually make the filter smaller and configure a filter with more unimodal characteristics. FIG. 6 compares the characteristics shown by the solid line when input terminal b is selected in FIG. 4 with the characteristics in a conventional configuration example. The dotted line in FIG. 6 shows the characteristic when the Tievisiev characteristic having equiripples in the attenuation region is constructed by the conventional method using 22 delay elements and 22 multipliers. Although the number of delay elements increases slightly, the required characteristics can be achieved without using large-scale hardware multipliers. When the attenuation amounts are 70 dB and 64 dB, Embodiment A of the present invention and the already proposed digital filter B without a multiplier (digital filter in which the weighting coefficient is approximated in pseudo-binary form by selecting the tap position of the delay element) (electronic communication Academic conferences, circuit and system research materials
Compared to CST76-98 "Synthesis method of digital filter for SSB terminal station" November 29, 1976), the number of delay elements and the number of adder inputs can be reduced as shown in the following table.

[Table] In the present invention, a digital filter means a filter that processes at least a temporally quantized signal. Therefore, a delay element can be constructed not only by a flip-flop but also by a charge transfer element. (CCD, BBD), etc. As explained above, since the present invention does not use a multiplier, the circuit configuration is simple, and since basic configurations of similar configurations are connected in cascade, it is easy to obtain a desired amount of attenuation. Since it is a cascade connection of similar patterns, it is easy to integrate it into an integrated circuit. In the digital filter of the present invention, the number of delay elements constituting the arithmetic circuit of the basic configuration is successively increased, which are connected in cascade to form the digital filter, and by increasing the number of cascaded arithmetic circuits. By gradually reducing the sidelobe level, it is possible to configure a filter with more unimodal characteristics.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional transversal digital filter, FIG. 2 is an arithmetic circuit of the basic configuration of the present invention, and FIG. 3 is an explanatory diagram of a cascaded configuration of arithmetic circuits of an embodiment of the present invention. ,, FIG. 4 is a block diagram of a digital filter according to an embodiment of the present invention, and FIGS. 5 and 6 are frequency characteristic curve diagrams thereof. _D1 ~ _DK-1 , _D11 ~ _D67 are delay elements, AD, _AD1 ~
AD ₆ is an adder.

Claims (1)

[Claims] 1. The basic configuration is an arithmetic circuit consisting of a delay circuit in which a plurality of delay elements each having a delay time of one word are connected in cascade, and an adder to which all tap outputs from the delay circuit are connected. A digital filter characterized in that arithmetic circuits having the basic configuration in which the number of arithmetic circuits is successively increased are connected in cascade.