JPS6130833A - data transmission equipment - Google Patents

Abstract

PURPOSE:To improve the transmission efficiency by dividing a storage means of a packet frame into a data information storage means and a control information storage means and providing plural number of control information storage means so as to eliminate timewise delay between packet frame transmitting means. CONSTITUTION:Data packet information of a data packet storage area 3a is stored in a transmission register 5. A data designated by a length counter 12 is transmitted from the transmission register 5. A register changeover circuit 14 switches an output of a multiplexer 7 into the information of a transmission register switching circuit 60 from the transmission register 5 by using a data packet transmission end signal 23 from the length counter 12. Special packet information stored in special packet storage areas 3b, 3c is stored in transmission registers 6a, 6b and this information is outputted from a multiplexer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a data transmission device in a network system, and more particularly to a data transmission device that stores packets to be sent out on a transmission path in different storage units for each packet and sends them out.

[Prior art] In a network system, "packet frame AJ
consists of a "data packet frame" for sending outgoing messages and a "special packet frame" for sending control information on the transmission path, and the "special packet frame" is - For example, the "token frame" in the token format.
There are things called. The transmission device needs to send out a "special packet frame" immediately after the "data packet frame" is sent out. Conventional transmission devices have the disadvantage that a blank time occurs between when the data packet frame J is sent and when the special packet frame starts being sent. That is, this is because it takes time to store the "special packet frame" information in the transmission register after the transmission of the "data packet frame" information stored in one transmission register is completed.

In addition, when there is only one control information storage section, when it becomes necessary to correct the contents of the control information storage section depending on the state of the device, it takes time to rewrite the control information, which further increases blank time and reduces transmission efficiency. There were drawbacks that made it worse.

[Objective] The present invention has been made in view of the above-mentioned drawbacks, and includes a separate storage means for each transmission information of a packet frame, and immediately after the data frame transmission network T from the data information storage means, one of the control information storage means It is an object of the present invention to provide a data transmission device which can selectively transmit a control information frame, eliminates any time delay between packet frame transmissions, and significantly improves transmission efficiency.

[Example] Examples according to the present invention will be described below with reference to the drawings.

FIG. 1 is a comparison diagram of the transmission time between a conventional example and an embodiment of the present invention.

In FIG. 1(a), if either the "data packet frame" sending time t1 or the "special packet frame" sending time L3 is the same, the "special packet frame" storage time t2 in the conventional example is completely eliminated in this embodiment. Therefore, the overall time for sending a "packet frame" can be shortened, and the efficiency of the transmission path can be greatly improved.

FIG. 1(b) shows a case where the transmission speed is even higher, and shows that in the conventional example, the proportion of the "special packet frame" storage time t2 increases. As is clear from the figure, the effectiveness of the device of this embodiment increases in the case of high-speed data transmission.

FIG. 2 is a block diagram of an embodiment of the device according to the present invention.

In the figure, 1 is a processing device, 2 is a receiving device, and 3 is a storage device. The storage device 3 includes a data packet storage area 3a that stores data packet (transmission message) information, and special packet information of different types (control There are special packet storage areas 3b and 3C storing information). 4 is a transmitting device, and the transmitting device 4 is composed of the following blocks. Data packet transmission register 1 (5), special packet transmission register 2 (6a), transmission register 3
(6b) , switching circuit 60 for transmission registers 2 and 3
, multiplexer 7, startup circuit 8, transmission register 1 (5
) address counter 1 (9), transmission register 2 (6a
) or address counter 2 of transmit register 3 (6b)
(10), P-S circuit 11, length counter 1 (12)
), a length counter 2 (13), and a register switching circuit 14. Further, 15 is a transmission line.

The transmission operation of the apparatus of this embodiment will be described below with reference to the transmission processing operation flowchart shown in Figure N43.

First, in step 30, the processing device (hereinafter abbreviated as CPU)
The special packet information stored in c is sent to transmission register 2 (
6a) and 3 (6b), respectively.

In step 32, the content of the information in the special packet frame is changed depending on the state of the CPU. That is, the special packet transmission register switching signal 30 is applied to the transmission register switching circuit 60 to select transmission register 2 (6a) or transmission register 3 (6b). Then, the process advances to step 34, and waits for the generation of transmission data. When the transmission data is generated and the transmission data is all stored in the data packet storage area 3a of the storage device 3, the process advances to step 36, and the data packet information is stored in the transmission register 1 (5). do. Next, in step 38, the length of the data packet is set in the length counter 1 (12), and in Stella 7'40, the CPU 1 issues a transmission start signal 20.
is output to the starting circuit 8 to start the transmitting device 4, and at the same time, the register switching circuit 14 sets the multiplexer output to output the data from the transmitting register 1 (5). Through steps 42 and 44, the startup circuit outputs the address count signal 22, and the address counter 1 (9
) and length counter 1 (12), and outputs the data packet information stored in the transmission register 1 (5) to the multiplexer 7. The multiplexer 7 is initially set to the transmitting register 1 by the register switching circuit 14.
The data in (5) is output to the P-S circuit 11. The data output to the P-S circuit 11 is converted from parallel to serial by the transmission clock signal 21 from the starting circuit 8, and the transmission signal 24
The signal is sent to the transmission path 15 as a signal, and is output to a transmission device connected to another transmission path.

Length counter 1 (12) from transmission register 1 (5)
When the specified amount of data has been transmitted (address count signal 22 is output), the process proceeds from step 44 to step 46, and the length counter 1 (12) outputs the data packet transmission end signal 23. In response to this data packet transmission end signal 23, the register switching circuit 14 switches the output of the multiplexer 7 from the transmission register 1 (5) to the information from the transmission register switching circuit 60. That is, the information from the transmission register 2 (6a) or the transmission register 3 (6b) is output from the multiplexer 7. At the same time, the sending address and length of the special packet are sent to address counter 2 (10) and length counter 2 (13).
Set it up and start it.

Then, in steps 48 and 50, the address count signal 22 from the startup circuit 8 is output, the address counter 2 (10) and the length counter 2 (13) are counted up, and the transmission register 2 (6a) or the transmission register 3 ( 6b) is output to the P-5 circuit 11 via the multiplexer 7, and
-5 circuit 11 outputs it to transmission line 15 as serial data transmission signal 24 in synchronization with transmission clock signal 21 . When the special packet data designated by the length counter 2 (13) is sent out, the process proceeds from step 50 to step 52, and the length counter 2 (13) outputs a transmission end signal 25 to the CPUI. Further, this transmission end signal 25 resets the starting circuit 8 and the address counter 1 (9). Then, the transmission process ends.

In this embodiment, two control information storage units 3b and 3c and two corresponding transmission registers 2 (6a) and 3
Although the case in which (6b) is provided has been described, the present invention is not limited to this, and depending on the possible states of the CPU 1, more storage units and corresponding transmission registers may be provided. Additionally, DMA may be used to transfer data from the control information storage section to the transmission register, but if the storage section and transmission register correspond, a read signal is given to the control information storage section by hardware and the transmission register is transferred to the transmission register. It is also possible to transfer data to the Send I8 register by providing a latch signal.

Further, although 3b and 3c are used as the control information storage unit (special packet information storage unit), for example, only one control information storage unit 3b is used, and the plurality of control information stored in the control information storage unit 3b is The packet may be transferred to the corresponding transmission register 2 (6a) or transmission register 3 (8b) by read/write control by the CPU 25 or by DMA. Similarly, one of the read data of the transmission register 2 (6a) or the transmission register 3 (6b) is selected and outputted by the consent circuit 60, but the switching circuit 60 selects and outputs the read data of the transmission register 2 (6a) or the transmission register 3 (6b). 6b
FIG. 4 shows a block diagram of a data transmission device having the above-mentioned configuration, which may select one of the transmission registers and send the read data of the selected transmission register to the multiplexer 7.

Operation control in this case is as follows. At step 30 shown in FIG. 3, the CPUI is stored in the special packet storage area 3b in the storage device 3. Each of the control information packets that the device can take is sent to the transmission register 2 (6a) or 3.
(6b).

This transfers a plurality of control information packets stored in the special packet storage area 3b to the corresponding transmission register 2 (6a
) or 3 (6b) using read and write signals from the DMA or CPU.

In step 32, the content of the sending frame of the special packet information is changed depending on the state of the CPU 1, that is, the state of the transmission device. That is, the special packet transmission register switching signal 30
is applied to the transmission register switching circuit (60) to select transmission register 2 (6a) or transmission register 3 (6b).

The subsequent processing from step 34 onwards is no different. Although the explanation has been given in which two types of control information packets are stored in the control information storage section 3b and each of them is transferred to the transmission register 2 (6a) and the transmission register 3 (6b), the present invention is not limited to this. However, depending on the state of the CPU, etc., the control information storage section 3b may store a large number of control information buckets) and be equipped with a transmission register corresponding to the number of pieces of information. good.

As explained above, in this embodiment, by providing the storage means for data packet transmission and the storage means for control packet transmission, there is no time gap between the two packet transmissions, and the same control packet can be repeatedly transmitted. This eliminates the need to generate and set control packets each time, such as when a data transmission device is used, making it possible to provide an extremely efficient data transmission device.

Furthermore, by preparing multiple special packet information frames, even if it is necessary to change the contents of some special packet frames while sending a data frame, it can be controlled by preparing registers that store several types of special packet frames in advance. without rewriting or resetting the packet,
The effect of providing a data transmission device that can cope with the problem only by switching registers is even greater.

[Effects] As explained above, according to the present invention, by dividing the packet frame storage means into the data information storage means and the control information storage means, and by providing a plurality of control information storage means, Even if some control information frame changes, it can be handled simply by switching the control information storage means without rewriting or resetting the control information, so there is no blank space between the transmission of data information and the transmission of control information. It is possible to provide an extremely efficient data transmission device that saves time.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are diagrams showing a comparison of data packet sending times; FIG. 2 is a block diagram of an embodiment of the present invention; FIG. 3 is a control flowchart of transmission processing in this embodiment; FIG. 4 is a block diagram of another embodiment according to the present invention. In the figure, l... processing device, 2... receiving device, 3...
Storage device, 4... Transmission device, 5... Data packet transmission register, 6a... Special packet transmission register 2
．． 6b...Special packet transmission register 3.7...Multiplexer, 8...Start circuit, 9...Address counter l, 10...Address counter 2.11...
P-5 circuit, 12...Length counter 1.13...
・Length counter 2.14...Register switching circuit,
15... Transmission path, 30... Transmission register switching signal, 60... Transmission register switching circuit. Patent applicant Canon Co., Ltd. Figure 1

Claims (2)

[Claims] (1) In a data transmission device that is connected to each other via a communication medium and performs data transmission by exchanging packets, the data information storage means stores data information, and the control information storage means stores at least two pieces of control information. , selection means for selecting one of the control information storage means, and control information stored in the control information storage means selected by the selection means subsequent to the data information stored in the data information storage means, to the communication medium. A data transmission device characterized in that it sends out and forms one transmission packet. (2) The data transmission apparatus according to claim 1, wherein the selection means changes the selected control information storage means according to the state of the data transmission apparatus.