JPS6132579A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the increase of parasitic capacitance and the formation of a parasitic MOS transistor by providing a process in which first and second silicon oxide films are shaped, a process in which a conductive layer consisting of polycrystalline silicon is formed selectively and a process in which the second silicon oxide film is removed selectively. CONSTITUTION:An silicon oxide film 42 is formed onto one conduction type single crystal silicon substrate 41, and an silicon nitride film 45 as a non-oxidizable film is applied onto the film 42. Photo-resists 44a, 44b are removed, and a first silicon oxide film 43 is shaped through oxidation treatment in an oxidizing atmosphere at a high temperature. A second silicon oxide film 46 is grown on the whole surface in uniform film thickness. A polycrystalline silicon film is applied onto the surface of the second silicon oxide film 46, and a conductive layer 47 is shaped onto an inter-element isolation region in a predetermined region. Polycrystalline silicon is applied in an element region, and a gate electrode 48 is formed through selective etching. Lastly, an insulating film 50 is shape, a contact section is bored in a prescribed region, and a conductive layer 49 is formed by aluminum, etc.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device with high precision, particularly an MO8 type semiconductor device with a small gate width that enables high-density integration. The present invention relates to a method of manufacturing a semiconductor device.

(Prior Art) High-density integration of MOa type semiconductor devices requires miniaturization of each semiconductor element that constitutes the device.
The miniaturization comes with manufacturing constraints. There are various manufacturing constraints, among which the most serious problems in conventional manufacturing methods will be explained.

FIG. 1 is a plan view of an example of a conventional MOa type semiconductor device.

A source/drain region 1.2t is provided in the element formation region of the silicon substrate 4, and a gate electrode 3 is provided through a gate insulating film.
By providing this, an MOB type semiconductor device is manufactured. In FIG. 1, W indicates the width of the gate electrode, and L indicates the gate length.

Figures IE2-) to (c) are cross-sectional views shown in the order of steps for explaining a conventional MOB type semiconductor device manufacturing method.

First, as shown in FIG. 2(a), a silicon oxide film 25 is formed on the entire surface of a negative conductivity type single crystal silicon substrate 21, and a silicon nitride film 26 is entirely deposited as an oxidation-resistant mask. Furthermore, after that, a photoresist 22 is formed.

Then, using a known photo-etching technique, the photoresist (22tFJ) is removed only at predetermined locations, and the photoresist at other locations is removed. Next, using the photoresist 22 as a mask, the silicon nitride film 26 is left only at predetermined locations and removed by a known etch method.

Next, as shown in FIG. 2(b)K, a photoresist 22
After T- removal, high-temperature oxidation is performed to form a thick silicon oxide film 24 on the surface of the silicon substrate 210 except for the areas covered with the silicon nitride films 26 a, 26 b, and 26 c.
a, 24b'e form.

Next, as shown in FIG. 2(C), the silicon nitride film 26
a, 26b, 26cff - remove. A region 23a where thick silicon oxide films 24a and 24b are formed,
Reference numeral 23b indicates element isolation insulating regions, and the area sandwiched between these regions becomes an element forming region. Next, a gate electrode 27 is formed at a predetermined location on the element formation region using a known photoetching technique.

On the other hand, on the element isolation insulation region 24b, a conductive layer 28 called a wiring layer is selectively formed in contact with the element isolation insulation region 24b, for example, for the purpose of connecting each element. Conventionally, syridine gate type MO8)
In transistors, the conductor layer 28 is often formed of polycrystalline silicon.

Next, impurity diffusion layers 29a, 29b, and 29c, which will become source/drain regions, are formed at predetermined locations on the surface region of the silicon substrate 21 using ion implantation or thermal diffusion.
, 29d. In this way, - source/drain regions are formed in the impurity diffusion layers 29a and 29b', and 27
The basic structure of an MOa-type semiconductor device having a gate electrode of 1 is obtained.

Next, an MO8 type semiconductor device is obtained by forming lead electrodes from the source/drain regions and the gate electrode, respectively.

With the manufacturing method of the MOa type semiconductor device as described above, L
When attempting to miniaturize semiconductor devices, that is, to manufacture semiconductor devices with small gate lengths and gate widths, serious limitations are encountered. Using the silicon nitride films 26a, 26b, and 26c shown in FIG.
When forming the silicon oxide film 26b, a phenomenon called bird's beak occurs, that is, the silicon nitride film 26a, 2
6b, 26C A kind of phenomenon of digging into the contents of the element forming area occurs from the periphery of the element forming area, so that the element forming area becomes smaller than a predetermined thickness.

In FIG. 3, the design values are used to indicate the design size of the element formation region on the 1ITtl photomask. Further, if the size of the element formation region after forming the silicon oxide films 24a and 24b as the silicon nitride film 26bt mask is klz, and the size of the bird's beak is Δt, then Δ
t is given by the following formula.

Δ'I=CL, x −1x )/2 The magnitude of Δt is specifically determined by the silicon oxide film 24a,
When the thickness of the film 24b is approximately 1 μm, Δt≧0.8 μm approximately. For example, when tl is about 5μ, At is 0.8
If we take the μ collection, tz≧3.4μ (), which is not a big problem, but if we reduce 11 to about 2μ, the silicon oxide films 24a and 24b will have the same lIt
If the film thickness remains the same, t2 is 2μ - 2×0.8μ groove, so 12≧0.4μ, and the manufacturing accuracy becomes very poor.

It is clear that the biggest cause of such a decrease in manufacturing accuracy is that the film thicknesses of silicon oxide IF, 24a, and 24b remain the same as the device is reduced. Therefore, in order to improve the manufacturing accuracy described above, it is necessary to
, 24b is best, but reducing the thickness of the silicon oxide films 24a and 24b risks deteriorating the performance of the device. Let me explain this next.

In the function of the semiconductor device, the silicon oxide films 24a and 24b have the purpose of electrically insulating and separating the elements of each MOS type transistor element constituting the semiconductor device. Another important function is the formation of a wiring region on the silicon substrate 21 utilizing electrical insulation from the silicon substrate. In FIG. 2(C), the conductive layer indicated by 28 is an example of such a wiring region.

The conductive layer 28 is formed in contact with the surface of the element isolation insulating region 24b. Here, the element isolation insulation region 24b
Let's consider reducing the film thickness.

Conventionally, the film thickness of the element isolation insulation region 24b has been determined based on the following two conditions.

(1) Preventing the formation of parasitic MOS transistors.

(2) Reduce the parasitic capacitance between the conductive layer and the silicon substrate.

The parasitic MO8) transistor in (1) refers to an element other than the originally designed MOS transistor that is formed between adjacent element formation regions using a conductive layer as a gate electrode. For example, in FIG. 2(C), 29c is 29a, 2
Impurity diffusion regions similar to 9b, but 29b and 29c
A MOS type transistor may be formed using the conductive layer 28 as a gate electrode as a drain impurity diffusion layer. Due to its nature, such MOS transistors formed outside the originally designed area are susceptible to parasitic MOS.
called a transistor. Inter-element isolation insulation region 24b
One of the purposes is to prevent the formation of such a parasitic MO8 transistor, and for this purpose, it is necessary to increase the thickness of the element isolation insulating region 24b.

Normally, the formation of a parasitic MOS transistor strongly depends on the potential applied to the conductive layer 28 and the impurity concentration of the silicon substrate 21. In the conventional example, if an appropriate impurity concentration is set, the threshold voltage of the parasitic MO transistor can be reduced to about 20 μm for a film thickness of 1 μm of the isolation region 24b.
VVc level can be set, which is the normal power supply voltage 5
This is a sufficient value for a semiconductor device of v. However,
When the film thickness of the inter-element isolation insulating region 24b is reduced to 0.5 .mu.m or less with miniaturization of devices, the threshold voltage of the parasitic MO8) transistor becomes less than lov, making it easier to form the parasitic MO8) transistor.

On the other hand, if the impurity concentration in the silicon substrate is increased, the threshold voltage of the parasitic MO8) transistor can be made sufficiently high even if the thickness of the element isolation region 24b is made thin; It is related to item 2). Next, this will be explained.

The conductive layer 28 is formed on the surface of the element isolation insulating region 24b, and when the entire semiconductor device is in operation, an appropriate potential is applied to the conductive layer 28, and the potential is applied to the silicon substrate. 21, charges are induced in the surface region of the region opposite the conductive layer 28. That is, a capacitor is formed between the conductive layer 28 and the silicon substrate 21. Such a capacitor, like a parasitic MOS transistor, is called a parasitic capacitor or parasitic capacitance. The increase in parasitic capacitance is
It does not affect the response time delay to a certain input signal to a semiconductor device in the form of an RC time constant.

Generally, the parasitic capacitance is the inter-element isolation insulation region 24b/7)I
IW IW Itr 諧h als7. [k −'/
II = ff y that is a term inversely proportional to the thickness of the depletion layer region extending into the interior of 91. To explain in more detail, the thickness of the depletion layer region extending into the silicon substrate 21 depends on the impurity concentration in the silicon substrate. It would be effective to reduce the parasitic capacitance by making the film thickness of the isolation region as low as possible and making the film thickness of the isolation region as large as possible. However, as mentioned above, in order to prevent the formation of parasitic MOS transistors, It is known that the impurity concentration in the silicon substrate should be as high as possible.In other words, when the film thickness of the inter-element isolation insulating region is made thinner with the miniaturization of devices, it is necessary to prevent the formation of parasitic MO8) transistors on the silicon substrate. The impurity concentration in the silicon substrate must be high, but in order to reduce the effect of parasitic capacitance, the impurity concentration in the silicon substrate must be as low as possible, which is a contradiction.

(Objective of the Invention) An object of the present invention is to provide a method for manufacturing a semiconductor device that can simultaneously prevent the formation of a parasitic MO8 transistor and prevent an increase in parasitic capacitance in response to miniaturization of elements. There's K things to do.

(Structure of the Invention) A method for manufacturing a semiconductor device according to the present invention includes a region in which an oxidation-resistant film is selectively formed on an element formation region on one principal surface of a silicon substrate, and a region in which an oxidation-resistant film is selectively formed on an element formation region on one main surface of a silicon substrate, and a a step of selectively forming a relatively thin first silicon oxide film in an inter-element isolation region not covered with a oxidizing film; and a step of vapor phase growth of a second silicon oxide film covering the first silicon oxide film. a step of selectively forming a conductive layer of polycrystalline silicon in a predetermined region on the second silicon oxide film on the element isolation region; The method includes a step of selectively removing the silicon oxide film.

(Example) Next, embodiments of the present invention will be described using the drawings.

FIGS. 4(a) to 4()I) are cross-sectional views shown in order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 4(a), a silicon oxide film 42 is provided on a single-crystal silicon substrate 41 of negative conductivity type, and a silicon nitride film 45 is deposited thereon as an oxidation-resistant film. Photoresist l-448, 44b is selectively formed thereon. Using this as a mask, the silicon nitride film is etched to form silicon nitride films 45a and 45b in the element formation region.

Next, as shown in FIG. 4(b), a photoresist 44
After removing 44a and 44b, oxidation treatment is performed in a high temperature oxidizing atmosphere to form a silicon nitride film 4Sa.

A first silicon oxide film 43 is formed on the surface of the silicon substrate 410 in a region not covered by the silicon oxide film 45b.

The thickness of the first silicon oxide film 43 is set to be thinner than the dimensions of the conventional device at an arbitrary reduction rate. The effect is particularly great when the film thickness is 0.5 μm or less.

Next, as shown in FIG. 4(C), a vapor phase growth method was applied to the entire surface.
The second silicon oxide film 46 is grown to a uniform thickness using, for example, a CVD method. Next, the second silicon oxide film 4
Polycrystalline silicon is deposited on the surface of 6, and a conductive layer 47 is formed on the element isolation region in a predetermined region using a known photoetching technique.

Next, as shown in FIG. 4(d), the second silicon oxide film 46 is removed by etching as a conductive layer 47tl-mask, leaving the second silicon oxide film 46a only in the region covered by the conductive layer 47. , the shape shown in FIG. 4(d) is obtained.

In this way, the thickness of the second silicon oxide film 46a can be increased so that the capacitance formed between the conductive layer 47 and the silicon substrate 41 becomes a sufficient ratio ζ. That is, the vertical dimension of the semiconductor device has been reduced, and in addition, a sufficiently thick insulating film (second oxide film 46a) has been formed in areas where parasitic capacitance is a problem, and parasitic capacitance has become smaller. ing.

In such a manufacturing method, the second silicon oxide film 4
When removing the silicon oxide film 43 by etching, the first silicon oxide film 43 formed below is also etched, and there remains a concern regarding the controllability of the film thickness.
Since the etching speed is significantly different between the silicon oxide film and the high temperature thermal oxide silicon film, there is almost no problem. For example, the etching rate of the silicon oxide film formed by the CVD method is about 3 to 4 times higher than that of the silicon oxide film formed by the CVD method. Therefore, it is considered that there is no problem in controllability regarding the etching i end point of the second silicon oxide film 46. On the other hand, silicon nitride films 45a, 45
Since b is hardly etched when normally etching a silicon oxide film, there is no problem in controllability in the silicon nitride film region.

Next, as shown in FIG. 4(e), the silicon nitride film 45
A and 45b are removed to form an element region.

Next, as shown in FIG. 4(f), polycrystalline silicon is deposited on the element region and selectively etched to form the gate electrode 48.
form.

When performing etching to form gate electrode 48, depending on the etching control conditions, etching may extend to the surface of polycrystalline silicon conductive layer 47 formed in the previous step. To avoid this, please refer to Figure 4 (
As shown in 2)), a coating 51 that is resistant to etching of polycrystalline silicon may be formed on the surface of the polycrystalline silicon conductive layer 470.

Finally, as shown in FIG. 4(h), an insulating film 50 is formed, a contact portion is opened in a predetermined region, and a conductive layer 491 is formed of aluminum or the like to form a polycrystalline silicon region for wiring. and electrical continuity with the gate electrode region.

(Effects of the Invention) As explained in detail above, according to the present invention, the MO8f
It is possible to reduce the film thickness of the inter-element isolation insulating region of an i-semiconductor device, and it is also possible to simultaneously prevent an increase in parasitic capacitance, which was considered unavoidable in the past, and the formation of a parasitic MOS transistor. A method for manufacturing a semiconductor device is obtained.

In particular, the isolation region between elements is thinner than before (approximately 0.5
The effect is great when the formation of

[Brief explanation of the drawing]

FIG. 1 is a plan view of an example of a conventional MO8 type semiconductor device, FIGS. The figure is a cross-sectional view for explaining the penetration of the silicon oxide film during the manufacturing process of a conventional MO8 type transistor.
Figures (a) to (h) are cross-sectional views shown in order of steps for explaining an embodiment of the present invention. 1.2...source/drain region, 3...-
-Gate electrode, 4...-Silicon substrate, 5--Conductor layer, 21...Silicon substrate, 22...
. . . Photoresist, 23a, 23b . . . Inter-element isolation insulating region, 24a. 24b...Silicon oxide film, 25...-
Silicon oxide film, 26 a, 26 b, 26
c...7 silicon nitride film, 27...-gate electrode, 28...-conductive layer, 29a. 29 b, 29 c, 29 d... impurity diffusion layer, 41... silicon substrate, 42...
...Silicon oxide film, 43...First silicon oxide film, 44a, 44b...Puffed resist, 45a, 45b...Silicon nitride film, 46,
45a... second silicon oxide film, 47...
...-conductive layer, 48... gate electrode, 49...
・・・Isoelectric layer, 5o・・・Insulating film, 51...
...Etching resistance; vague. Rod 1st 3rd figure Kaya 2 Figure rod 4th figure

Claims (1)

[Claims] A region in which an oxidation-resistant film is selectively formed on an element formation region on one main surface of a silicon substrate, and a region where an oxidation-resistant film is thermally oxidized using the oxidation-resistant film as a mask to separate elements not covered by the oxidation-resistant film. selectively forming a relatively thin first silicon oxide film in the region; and a second silicon oxide film covering the first silicon oxide film.
a step of forming a silicon oxide film by a vapor phase growth method; a step of selectively forming a conductive layer of polycrystalline silicon in a predetermined region on the second silicon oxide film on the element isolation region; A method of manufacturing a semiconductor device, comprising the step of selectively removing the second silicon oxide film using a conductive layer as a mask.