JPS6142839U - 集積回路パツケ−ジ - Google Patents

集積回路パツケ−ジ

Info

Publication number
JPS6142839U
JPS6142839U JP1984127279U JP12727984U JPS6142839U JP S6142839 U JPS6142839 U JP S6142839U JP 1984127279 U JP1984127279 U JP 1984127279U JP 12727984 U JP12727984 U JP 12727984U JP S6142839 U JPS6142839 U JP S6142839U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit package
bonding
circuit chip
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984127279U
Other languages
English (en)
Inventor
武夫 吉川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1984127279U priority Critical patent/JPS6142839U/ja
Publication of JPS6142839U publication Critical patent/JPS6142839U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】 第１図は本考案の一実施例に集積回路チップを収容した
状態を示す断面図、第２図は従来のパッケージに集積回
路チップを収容した状態を示す断面図である。 １，１．１−・・パッケージ基体、２， ２．ａｔ ２
ｂ−チップ収容凹み空間、３・・・ボンデイング端子、
４・・・チップ電極、５・・・金属細線、６・・・蓋、
７・・・封止ガラス、８・・・リード端子、９・・・突
堤、１０，１２，１３・・・集積回路チップ。

Claims (1)

    【実用新案登録請求の範囲】
  1. 集積回路チップを収容固着するための複数箇所の凹み空
    間を有し、さらに、前記隣り合う凹み空間の間の突堤上
    に、・前記集積回路チップのボンデ、 イング電極と接
    続する金属細線を接続するボンデイング端子が設けられ
    たパッケージ基体を備えたことを特徴とする集積回路パ
    ッケージ。
JP1984127279U 1984-08-22 1984-08-22 集積回路パツケ−ジ Pending JPS6142839U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984127279U JPS6142839U (ja) 1984-08-22 1984-08-22 集積回路パツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984127279U JPS6142839U (ja) 1984-08-22 1984-08-22 集積回路パツケ−ジ

Publications (1)

Publication Number Publication Date
JPS6142839U true JPS6142839U (ja) 1986-03-19

Family

ID=30685927

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984127279U Pending JPS6142839U (ja) 1984-08-22 1984-08-22 集積回路パツケ−ジ

Country Status (1)

Country Link
JP (1) JPS6142839U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0315548A (ja) * 1989-06-14 1991-01-23 Sekisui Chem Co Ltd 真空密着成形方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0315548A (ja) * 1989-06-14 1991-01-23 Sekisui Chem Co Ltd 真空密着成形方法

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