JPS6142862B2 - - Google Patents

Info

Publication number
JPS6142862B2
JPS6142862B2 JP54066409A JP6640979A JPS6142862B2 JP S6142862 B2 JPS6142862 B2 JP S6142862B2 JP 54066409 A JP54066409 A JP 54066409A JP 6640979 A JP6640979 A JP 6640979A JP S6142862 B2 JPS6142862 B2 JP S6142862B2
Authority
JP
Japan
Prior art keywords
vibration
semiconductors
ultrasonic
lead frame
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54066409A
Other languages
English (en)
Japanese (ja)
Other versions
JPS55158651A (en
Inventor
Isao Maeda
Keiji Hazama
Mitsuyoshi Nakatsuka
Shinichi Oota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP6640979A priority Critical patent/JPS55158651A/ja
Publication of JPS55158651A publication Critical patent/JPS55158651A/ja
Publication of JPS6142862B2 publication Critical patent/JPS6142862B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lining Or Joining Of Plastics Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP6640979A 1979-05-28 1979-05-28 Molding method for package of semiconductor Granted JPS55158651A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6640979A JPS55158651A (en) 1979-05-28 1979-05-28 Molding method for package of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6640979A JPS55158651A (en) 1979-05-28 1979-05-28 Molding method for package of semiconductor

Publications (2)

Publication Number Publication Date
JPS55158651A JPS55158651A (en) 1980-12-10
JPS6142862B2 true JPS6142862B2 (2) 1986-09-24

Family

ID=13314961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6640979A Granted JPS55158651A (en) 1979-05-28 1979-05-28 Molding method for package of semiconductor

Country Status (1)

Country Link
JP (1) JPS55158651A (2)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6263449A (ja) * 1986-08-01 1987-03-20 Hitachi Ltd 半導体装置の製造法

Also Published As

Publication number Publication date
JPS55158651A (en) 1980-12-10

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