JPS6145331A - Random number generating circuit - Google Patents

Abstract

PURPOSE:To increase the overall degree of integration of a random number generating circuit by adding a multiple to the contents of a memory for random number memory by an adder each input of a shift pulse and feeding a feedback signal to a carrier input terminal of the adder based on the output of said random number memory. CONSTITUTION:A random number generating circuit contains a shift pulse output pare 20 which delivers a shift pulse SP and a random number generating part 22 which produces a prescribed random number every input of the pulse SP. The part 20 adds the frequency data stored in a frequency data memory 24 to the totalized value B stored in a totalization memory 26 through an adder 28. This added value is used as the new value B to replace the contents of the memory 26. The part 22 consists of a shift circuit 32 serving as a shift register and a feeding circuit 12 which supplies the serial signals to the circuit 32 according to the parallel output of the circuit 32. The circuit 32 contains a random number memory 34 and an adder 36.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a random number generation circuit, and particularly to an improved random number generation circuit capable of obtaining a random number signal with a simple configuration. 1 Seikyu technology] Percussion instruments using electronic circuits? ? In order to create sound effects, etc. for games, a source for outputting random numbers is required, and for this reason various random number generation circuits have been developed and put into practical use. Figure 2 shows such a conventional random number generation circuit.a
3. The disturbance failure circuit 1 of ξ, which is not shown in FIG. and a feedback circuit 12 for inputting a predetermined serial number fc7 to the register. And shift pulse output circuit 14
When the shift pulse SP is input from the feedback circuit 12 to the shift register 10, a new serial signal sequence is input from the feedback circuit 12 to the shift register 10, and the memory contents are synchronized rightward in the figure. is occurring. Figure 2 (8) shows the power section of such a conventional random number generation circuit.
The specific circuit configuration of the circuit is shown, and the random number generation circuit of the embodiment includes an n-stage shift register 10 and a feedback circuit 12 to which a desired parallel output is manually input from the shift register 10. 24'' to 1 [Pseudo-random numbers with one tick period are stored in the shift register 10 (two-shot operation). Therefore, the contents of any stage of the shift register 10 are output and retrieved, and 0 An irregular random number sequence with Therefore, in actual use, K can only be used even if it is regarded as the same as a true random number. Therefore, by using the random number obtained in this way as a sample ring address, the desired noise signal can be output. Zuru becomes OI Noh.

[Invention tries to solve the problem! Problem 1 However, in the conventional random number generation circuit, it is necessary to provide the shift register 10 and the shift pulse output circuit 14 that supplies shift pulses to the shift register 10 independently. The number of points is large, the whole device is lj sloppy, and 12
There was a drawback that the i-valent one would get yelled at. In particular, in the sound generation circuit 113 that uses an electronic circuit to turn the sound of ``I'' into light, a desired pseudo 74 is added in addition to the random number light circuit for generating cone and waveforms. The periodic waveform light 81r'Il path for emitting the light by 1° is shown in a stage.Therefore, such a conventional random number light 41 circuit can be replaced with a periodic waveform light! If provided separately from one circuit, the entire circuit would be extremely complicated and expensive, and the entire circuit would have the disadvantage of becoming very bulky. [Objective of the Invention 1 The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to increase the degree of integration of the entire circuit, make it compact and low-cost.
The objective is to provide a one-stroke random number fe 4+ 1jil path. Means and operation for solving problem E] In order to achieve the above-mentioned object, the circuit of the present invention has a cumulative memory that stores the cumulative value, and a cumulative value that stores the cumulative value and externally inputted frequency data. a first adder for inputting and storing the additive value of the parasitic element as a new cumulative Q value in the cumulative memory, and occurs when the cumulative Q value of the first adder overflows. It consists of a shift pulse output section that outputs a shift pulse according to the carry signal, a random value memory, and a second adder, and a second adder is used to add the contents of the random value memory to one sentence in which the shift pulse is input manually. A shift circuit functions as a shift register by updating with multiple decoration, and the w is based on the output of the random value memory.
9 to the carry input terminal of the 42 adder? a feedback circuit that feeds back the D-far signal, and a random number generator that generates a predetermined random number in the random value memory, the first adder and the second adder having the same adder. n
The feature is that the equipment can be shared in a time-divided manner. With the above configuration, the random number generation circuit of the present invention can reduce the number of parts used and increase the degree of integration of the entire circuit. As a result, it is possible to generate random numbers with a small size and a low The circuit can be provided. Here at J3, it is possible for the random number generation circuit of the present invention to be widely used in each village. It is suitable as a random number generation source to be used when generating noise in a sound generation circuit. [Embodiment 1] Next, a preferred embodiment of the present invention will be described based on the drawings. (A> Original of random number generation circuit Jn1 In FIG. 1, a preferred embodiment of the random number generation circuit according to the present invention is omitted. The random number generation circuit of the embodiment outputs a shift pulse 81). The output unit 20 generates a predetermined random number each time the shift pulse SI) is input.
and a random number generator '22. The shift pulse output section 20G inputs the frequency 1 stored in the memory 24 and the accumulated value 3 stored in the main memory 26 to the adder 28. Then, the decoration value is set as a new cumulative 0 value B, and the metric contents of the cumulative memory 26 are updated. This update of J: unaccumulation g>me 26 is performed every time a write pulse a is input from the timing generation circuit 30 at a constant period. Therefore, the shift pulse output section 20 of the embodiment adds the cumulative sieve value stored in the cumulative memory 26 and the frequency data F etc. output from the frequency data memory 24 by the operation of the lead generator 28, and If the light pulse a is output from the generation circuit 30, the added Q value is stored in the cumulative numbing meter 26 as a new cumulative value. is the cumulative value B and the frequency data]: When this decoration value exceeds 20-, the digit J-off signal C is output from the output terminal r-CO, and the result is as follows. The carry signal/signal CS outputted from the t-timing generation circuit 30 is supplied to the I-31 along with the timing (F'; It is output from the node gate 31 as a shift pulse SP. In this manner, the shift pulse output unit 20 of the embodiment outputs a shift pulse S to the random number generation unit 22 when the decorator 28 outputs an overflow [''-S digit-[C]. The time interval at which this shift pulse SP is output is
``> device 28 is open/closed for 16 hours overflow, therefore, if the value of the frequency data `` manually entered into the addition nn28 is large, the time interval can be shortened, and by decreasing the value of 1: The time interval can be lengthened by °C. Therefore, by setting a larger value for the frequency 1!:inclusive memory 1 in the frequency counter 24, A shift pulse SP is output from the shift pulse output unit 20 at short time intervals, and by setting a small frequency data in the frequency counter 24, the time interval of the output shift pulse S IJ is changed. In addition, the random number light unit 22 of the embodiment performs a serial shift operation based on the parallel outputs of the shift circuit 32, such as a shift register 32, which also functions as a shift register. 91g to the shift circuit 32. The shift circuit 32 includes a random value memory 34 and a second
It consists of an adder 36, and every time a shift pulse SP is input from the shift pulse output section 20, the second adder 36 is used to add a multiple to the contents of the random value memory 34 and update the memory contents to new memory contents. . In the embodiment, the second adder 36 functions as a doubler that doubles the contents of the random number value Mepiry 34. By doing this, the memory contents stored in the random value meter 34 will be changed to 1 when the shift pulse SP is input manually.
It functions as a shift register by shifting to the upper digits in sequence. For example, if the memory contents of the random value memory 34 are ro
If the 9m return value of the g-luck circuit 12 is rOJ in ollJ, and the memory contents are added to the second storage unit 36 by J:, the contents become 10110. Furthermore, when this new memory content "0110" is further multiplied by the controller 3'6, the memory content becomes "1100".
It becomes J. In this way, the shift circuit 32 opens in the same way as a shift register. A predetermined serial signal is output as ; to i', and the serial signal is manually inputted to the key 1 of the second input unit 36.Here, the key 1 input is The end C1 becomes equivalent to the input of the genomiy register (Purushiri)/le. By doing this, the random number generation section 22 of the embodiment is completely identical to the J route shown in Figure 12. It functions similarly, and can generate a random number inside the random value memory 34 every time the shift pulse SP is input. At this time, the random number generation cycle is determined by the shift pulse supplied from the shift pulse output section It is determined by the output period of S P, and therefore, by making the frequency data written and stored in the frequency data memory 24 large, the random number generation period can be set short, and the frequency data to be set can be made small. By doing so, it is possible to set the random number generation period to be long:''. As explained above, the random number source 1 circuit according to the present invention has a circuit configuration that approximates the shift pulse output section 20 and the random number generation section 22. The characteristic feature is that by using the IL'1 division method, the first booster 28 and the second booster used in the cis]-pulse generator 20 and the random number generator 22 are 36, the same adder is used for 11 functions.In other words, the shift pulse output section 20 is
By performing the operation of the first adder 28 and the operation of the random number generator 22 at different timings, the first adder 28 and the second adder 36 are operated at the same time (there is no need to operate them twice). , one adder is used as the first adder II 28 when the shift pulse output section 20 is operating, and as the second adder 36 when the random number generator 22 is operating.
By using the same adder as the first and second adders 28 and 36 in this way, the configuration of the random number generation circuit can be simplified and its degree of integration can be increased. The overall cost can be reduced. In addition, in the random number generation "] path of the present invention, the shift pulse output section 20, the random number light section 22, and the memory 2
4, 26.34, and 1111-1 can be used to store these memories 24°26.34 and 1111-1.
It becomes possible to form the memory at different addresses in a RAM, for example, and by doing so, it becomes possible to further increase the degree of integration of the entire circuit. , Cow times Next, in Embodiment 1, which will be explained by taking as an example the case where the random number generation circuit of the present invention is applied to a sound generation circuit, this sound generation circuit number will be used to generate a waveform of arbitrary frequency and shape. It includes a periodic waveform generation circuit that outputs a desired onomatopoeic sound and a noise waveform generation circuit that outputs a noise waveform of a desired period and generates, for example, the sound of a percussion instrument or the sound effect of a game. , random number light 4 of the present invention
The F circuit is used as part of the noise waveform generation circuit. In the following, the n generation circuit of the embodiment will be explained in terms of periodic waveform light, one circuit, and noise waveform generation circuit. (B-1) Periodic waveform generation circuit FIG. 3A shows a preferred embodiment of the periodic waveform generation circuit.
By reading out the breath waveform at a desired cycle from a plurality of waveforms pre-stored in the internal memory, a waveform of an arbitrary frequency and shape can be generated.As is well known, the general waveform is: It has three elements: waveform (shape), repetition frequency (period), and amplitude, and if any of these differs, the waveform will be different. For example, in the case of onomatopoeia, the timbre, pitch, and sound pressure will be different. Note that the above frequency also includes the initial phase.
3, each element is arbitrarily designated, and by selecting the waveform stored in the waveform memory 40, the waveform is determined, and by setting the readout frequency division ratio of the selected waveform.
1 frequency (period and initial phase) is determined. i °(,
After these waveforms and frequencies are digitally specified, their amplitudes are set. The characteristic feature of the frequency 1!11 waveform generation circuit of the embodiment is that the waveform selection and the readout frequency division ratio are processed separately, and in particular, the readout frequency division ratio is determined by the readout frequency (period). It is possible to set any frequency just by inputting it externally, and even though the memory of the waveform memory 40 is limited; it generates a large number of waveforms!IL
It has the advantage of AEi. Hereinafter, details of the periodic waveform generation circuit of this embodiment will be explained. In embodiments, waveform memory 40 is a ROM or ItA
A plurality of waveforms are stored inside the waveform memory 40. Table 1 shows an example of the waveforms stored in the waveform memory 40. The waveform stored in the waveform meter 40 in this manner is selected by a waveform number S, which is supplied from a waveform selection meter 42 and is made up of 4 with 4-bit numerical data, and the selected waveform is 1. The waveform data is outputted as data for a wavelength. The waveform data is sequentially outputted in a predetermined number based on the readout number of data for one wavelength, L, and the sampling address 1 yen supplied from the 43 periodic address output circuits. In the embodiment, this periodic address output circuit 43 is composed of a frequency meter 44, an accumulation memory 46, and a decorator 48, and the above-mentioned waveform memory 40 The readout cycle of the waveform that is changed by a selected amount from 1 to 2 is determined by the frequency data F supplied from the frequency memory 44.
“The initial phase of this readout frequency is
6 is written and stored by an initial phase setting circuit not shown in the figure. That is, the circuit of the embodiment has an accumulation memory 46 and a memory 11.
s48, an accumulator is formed, and the decorator 48 adds the frequency data F supplied from the frequency memory 44 and the accumulated value B accumulated and stored in the accumulating memory 46, and calculates the frequency data W. +), an update operation is performed to update the memory contents of the cumulative memo 946 as a new cumulative 9) value. Therefore, the cumulative data 13 in the element memory 46 increases in the order of the number of frequency data supplied from the frequency menu to the number of pulses WP supplied. Then, this cycle 1/1 waveform generating circuit supplies new accumulated data [3] to the waveform memory 40 as a sampling address signal in the accumulated Q memory 46 every time the update operation is performed. . (Then, from the waveform selected by the waveform limber S, the waveform data specified by the accumulated data B is read out and the sampling operation is performed.) For example, the frequency data F is set to 20 bits and the cumulative n value B is set to 21 bits in order to increase the frequency accuracy by 1. However, the waveform data selected by the cumulative value B is 2a Word Pi 1 ~ Izumi is not necessary, only the 1st 5 bits of B (B is 2'-' = 6
Sa>+, which is obtained by dividing by 5536 and rounding down the decimal places, is used as sampling address information and phase angle information. Therefore, the waveform data read from the waveform memory 40 is 2S=32 words. Each word read in this manner indicates the amplitude of the waveform. Since one word of the waveform 5'-data has 4 bits, one waveform data has 32×4=128 pits. In addition, the waveform limber S has 4 bits and can register waveforms of 16 seconds, so the total waveform memory is 12°8.
Pit x1 (3 = 2048 bits. Table 2 shows only the cumulative data B for each summing for one type of waveform and an example of the waveform γ-Y output from the waveform memory 40. There is.No (n=o
, 1, 2, 3, 4. -) is the memory J representing the (n4th rimbling), and SDo in the waveform data column is the output waveform data based on Table 1 in the case of waveform number S-〇.
SD-7 shows the output horn waveform data based on Table 1 when waveform number 3=7. Here, the frequency data F in the initial state is F=
010000H, and the accumulated data is assumed to be 13eB-OOH. Here, the digit 1 at the end is shown to indicate that the 15 digits are hexadecimal numbers. First, it is assumed that the waveform S=O++ is selected by the waveform non-bar S. , in the case of simbling NO, the waveform number is 4; since L S = OH, the waveform memory 40
The top 4 address pits of are oooo, and the accumulated data B i is [3=OOOH, so the waveform memory 40
The address root position 5 pit becomes ooooo, and from the waveform memory 40, o o o o o o o o o O!
The waveform data 1-7 specified by the 7 address of J' and OOOH is sampled and read out. Similarly, for °rimbling N1, 5=01-1
1 accumulated data 85 pits is 0111, so the waveform data "9" at 00111, where the address root 4 bits and ] and 5 bits are 0000 and 00001, respectively, is read out for sampling. . In this way, the cumulative data B is sequentially updated one by one, and the result is > data B's [-! ′
The 5 bits change sequentially as shown in Table 2 each time each sampling operation is performed, and the waveform data S=01)1 selected in Table 1 is sequentially sampled and read out at predetermined intervals. FIG. 13 shows an output waveform diagram of the waveform selected by the waveform number S = OI-1, and as is clear from the figure, when the waveform is selected by S = OH, sin
It can be seen that a waveform is obtained. 33 in the same figure, the horizontal axis represents the number of sampling times, and the vertical axis represents the ablation of the sampled waveform data.
Although the case where the in waveform is selected has been explained as an example, the periodic waveform light-1 circuit of the embodiment is not limited to this, and other waveforms can also be selected. For example, if the waveform is selected by waveform number 5=IH, What is shown in column 50-7 of Table 2 <S-1'
The waveform data of the waveform selected by ll is sequentially sampled and read out. FIG. 14 shows the waveform sampled and read out in this way, and as is clear from the figure, S=
It can be seen that harmonics are output when the waveform is selected by -7H. As described above, according to the periodic waveform generation circuit of the embodiment, it is possible to arbitrarily select and output the 7j waveform selected by the waveform number S from a plurality of waveforms preset in the waveform memory 40, Therefore, by simply presetting an appropriate waveform in the waveform memory 40 and setting J3<
A desired waveform can be output. Next, the readout frequency of the waveform sampled and read out in this manner is determined by d·1. Focusing on the value of cumulative data B in Table 2, the initial state is N. The value of 8 at the time of and the value at the time of N20 are snowy. This is the same as the first 391 state (when the value of 3 changes from N=0 to 201-1 cycles after which the bone generator 48 overflows and the waveform becomes 391). This means that the period has returned to 7, and the periodic waveform is outputted during these 20 II 'J cycles. The period corresponding to this one wave is defined as [1 period 1]. In this example, the entire IP'D data 13 (21 bits)
The period during which the value of increases by 2000001-1 is one cycle. However, the number of recycles required to divide the waveform for one period by 1j7 changes depending on the value of the frequency data F. Of course, if you know the interval of increase in the cumulative Q data F4, you will need a large number of sampling cycles to obtain one period's worth of waveform, but if you change it, you can obtain one period's worth of waveform with a small number of sampling cycles. . Here, if the number of simbling cycles that occur during one cycle is NS, and the number of pits in accumulated data B is H, then N N5 = □ ... (1) [ A roar. The time required for 11 IC samplings is 1
In other words, the time required for 1" rimbling cycle is [8
If the time related to the 11th lap IUJ is TS, 'rs -N
This becomes the sth tS. Therefore, the frequency of the output waveform is 1 1 F f= −= −= −−] (2) TS
N5-ts t:;・2, where ts is a constant, so the frequency of the output periodic waveform is determined by 1+fIF of the frequency data. It will be appreciated that the frequency ``can be set to A:F depending on the value of the frequency data 1.'' In this way, the reading period of the periodic waveform from the waveform meter 40 is the frequency set in the frequency meter 44. Data 1-
When the value of F is large, it can be short, and when the frequency data F is small, it can be shortened. If we consider the case where waveforms are read out not shown in Table 2, in Table 2, waveform data is sequentially read out every 11° combining cycles. The value 010000H of t1 frequency data 1 is smaller and the top 5 of accumulated data B are selected at the end of one cycle of sampling operation.
If there is no change in the contents of the pit, the value of the waveform data simbling output from the waveform menu 40 also does not change. On such a platform, the core data [1st place 5th of 1]
As the sampling operation is repeated several cycles until the contents of ~ change, the output frequency of the periodic waveform becomes lower. Conversely, if the value of the frequency f-tar F is larger than oiooooo++ and the value of the upper 5 bits of the cumulative data B is accumulated for 02H or more in one sampling cycle, the waveform data becomes
Read out in an interlaced manner. . In this case, the output frequency will be higher, but the harmonic components of the waveform will be impaired. As explained above, in the periodic waveform generation circuit of the embodiment, it is possible to set the desired waveform number S and frequency data F in the waveform selection memory 32 and frequency memory 44, and therefore, the desired waveform number S and frequency data F can be set in the waveform selection memory 32 and the frequency memory 44. Depending on the settings, it is possible to generate any waveform from the waveform memory 40 at any frequency. Although the case where one periodic waveform is outputted by the periodic waveform generating circuit has been described in 1, it is also possible to obtain a periodic waveform by combining a plurality of waveforms by using the method of dividing into 10 time-separated waveforms. In this case, as the number of channels increases due to multiplexing,
The limp frequency per each y-1/channel will be low, but this sampling frequency should theoretically be set to a frequency that is at least twice the upper limit of the frequency band required for the output waveform. be done. The above-mentioned time-division sampling is performed cyclically for each channel, and the main sampling is performed by performing predetermined filtering on the waveform outputted via the DA':I inverter and removing frequencies outside the necessary frequency band. By using the circuit of the example, a complete composite waveform can be generated from the periodic waveform of multiple channels.
1 becomes r+711. In the periodic waveform generating circuit of the embodiment, each memory is formed at a different address in a predetermined storage element, for example, a RAM. <B-2> Miscellaneous sound waveform generation circuit The noise waveform light 71 circuit of the embodiment uses the above-described random number generation circuit of the present invention in place of the periodic address output circuit 43 of the periodic waveform generation circuit shown in FIG. 3A. By using the random number address output circuit in conjunction with the random number address output circuit, any waveform can be synchronized at a predetermined period from a plurality of waveforms stored in advance in the waveform memory 40, and a randomly shaped noise waveform can be read out at any frequency j This is what makes it emit. FIG. 3B shows such a noise waveform generation circuit according to the present embodiment, and the circuit according to the embodiment generates an arbitrary waveform stored in the waveform memory 40 according to the waveform number S supplied from the waveform selection memory 42. is selected and the selected waveform is generated using the random number generation circuit of the present invention at the sampling address (
Random numbers) The random numbers supplied from the address output circuit 45 are read out and output 8 at random. That is, the random number generation circuit of the present invention forming the random number address output circuit 43 supplies random numbers at predetermined time intervals, and the thus supplied random numbers are supplied to the waveform memory 40 as a sampling address signal. According to
From the waveform memory 40, waveform data specified by a random number is sampled and read from the waveform selected by the waveform number S. Therefore, the waveform data sampled and read out in this manner is the same as when the periodic waveform was sampled and read out, and since the sampling address changes randomly, the entire waveform data is - (noise where the waveform changes randomly). This will be output as a waveform. In this embodiment, such a random number address output circuit 4
Set the random number output from 5 to IG+GO], and set the predetermined ! of this 16-bit random number! ) Only the pits are supplied to the waveform memory 40 as sampling addresses. In addition, in the above explanation, 1 sound waveform 1! of the embodiment is used. The explanation has been given using the case where one 98' waveform is outputted by the g-circuit, but the noise waveform generation of the embodiment! +[il path can also be used to synthesize a 21[\S waveform] which is obtained by synthesizing a plurality of waveforms by using the method of time-separated waveform/C conversion as in the above-mentioned periodic waveform light ζ1- circuit. *', (13°) A 5. : /A fsil (J
) $'J ts't (q −j: Jlt the
The two characteristic steps of this embodiment are the operation of the periodic waveform light generation circuit and the operation of the waveform generation circuit at different timings, so that the same adder can be added. It is possible to perform the periodic waveform generation operation and the noise waveform light q operation by using the same waveform memory 40 as the periodic waveform generation circuit and the noise generation circuit. In this way, by sharing the loader and waveform memory used in the periodic waveform generation circuit and the noise waveform generation circuit (one circuit), the overall circuit configuration is simplified and its length is increased.
F! The cost of the entire device can be reduced. Next, a specific example of a circuit formed by combining the periodic waveform generation circuit shown in No. 358 and the noise waveform generation circuit shown in FIG. Let's discuss an example. (C) Specific Example Figure 4 shows the generation of periodic waveforms! A circuit is shown that can arbitrarily switch between the functions of i and noise waveform generation.The circuit of the embodiment has 16 channels, and one of each f-p channel
You can freely switch between the two C1 functions for each one. In addition, the circuit of the length/111i example is based on the periodic waveform generation circuit shown in No. 358 and the random number generation circuit shown in FIG. 3B.
Although the combination ``C'' is formed in U-, each of the circuits shown in FIGS. l! The circuit configuration shown in the figure is therefore somewhat different from that of the present embodiment. In the circuit of the embodiment, the RAM 50 is
+WE not shown in Figure 3A and Figure 3B in different addresses of +WE 2/l, 26, 34, 42,
44. 46 is formed. The memory area formed in this way is known as 4 sound ports, and in the embodiment, the sound port at the time of periodic waveform generation and the land port at 11 o'clock when the noise waveform is generated are fixed for each channel. has one rear of 8 bytes. Figure 5A shows the memory contents of such a soundboard. Figure 5A shows the soundboard used when generating periodic waveforms, and Figure 5B shows the soundboard used when generating the 911 I'p waveform. This shows the contents of the boat. J3, each of these 1 small round board h k 2 J31 = data symbols are the same as those used in Figure 1, Figure 3 A, and Figure 3 8). There is. 558th J3, frequency data F and cumulative data B
are respectively FO, Fl, F2 and LIO from the do position side.
, B1, and [12, each of which is divided into three parts and stored in the soundboard. As explained in FIG.
Data F and B stored in the memory are each 20 bits,
21 bits, whereas the adder 52 used in the circuit of the embodiment shown in FIG. 4 is 8 bits. This is because the decoration cannot be applied unless it is divided. J3, the decoration of the frequency data F and cumulative data B explained in FIG. 3 is performed sequentially from the do position side of each data shown in FIG. be exposed. - Furthermore, in the sound boat for noise waveform generation shown in FIG. It is divided and stored in SR1. This is because the memory capacity of the random value memory 34 is 16 bits, while the adder 36 has an 8-bit adder bit.
L/It depends on the fact that it doesn't exist. Also, data GO, G'N, which is not shown in FIG. This gain is outputted from the sound board of the RAM 50 at the time of outputting the waveform data from the waveform memory 40 shown in FIG. The signal is multiplied by the waveform data read out and output as an analog signal. Therefore, the amplitude of the waveform data read from the waveform memory 40 is controlled by this gain. In the embodiment, GO is normally used as this gain, but when outputting a stereo waveform, for example, it is also possible to adjust the amplitude of the waveform using gain G1 independently of this gain Go. In the tl-sound boat J3 shown in Figure A, [3, N is a data bit that switches the function of the circuit between periodic waveform generation operation and noise waveform generation operation, and this N
The channel whose function is switched by 1) is not the channel corresponding to the sound bottom where the N exists, but the next channel to be sampled. This is because data N is read at the end of one thin/ring process. In the embodiment, sound ports shown in FIGS. 5A and 8 are formed in the RAM 50 as described below. In accordance with a predetermined program, the CPU performs time-sharing access to i-Yu from each of these sound boats in synchronization with the CPU bus cycle. That is, one sampling process of one channel 1P channel in the embodiment is divided into four processes to perform time-division access to the RAM 50, and therefore,
In the circuit of the embodiment, in order to complete 16 channels of rimbling, 4X1B-=64. It is necessary to perform time-sharing access with 564 line periods. Next, the operation of the circuit shown in FIG. 4 will be divided into periodic waveform generation operation and jllll waveform generation operation, and the sampling process will be explained. In performing such an operation, there are intermittent periods in which μG )) tJ occupies the RAM 50, but in this embodiment, the multiplexer 58, which is in charge of time division of RAM addresses, selects channels and ports. The explanation of the RAM occupation period of CPtJ will be omitted, assuming that it is set on the 4rJ side. (C, -1) Periodic waveform generation operation First, the operation for generating the periodic waveform by the circuit shown in FIG. 4 will be explained. As shown in the ItI L!n of the circuit, as shown in FIG. 5A-!J'
4) ■Kundo port frequency data [- and? 7:
eEi (114 days, riB and σ are accumulated, and then an arbitrary waveform is read out from the waveform memory 40 based on the accumulated result, and after ・, the gain Go of the sound boat shown in FIG. 5 is The waveform amplitude is determined by I) A T, I
A log waveform is output from the server 56. Hereinafter, this waveform generation operation will be divided into the main operation of the frequency 1-data F and the basic data RI-B, and the operation of reading out the periodic waveform from the waveform memory 40 based on this cumulative effect. explain. First, this waveform data and the 9A reed value data B are accumulated using the decorator 52 as the adder 48 shown in FIG. It is performed in three blocks: I F30, second 11+81, and third F2+82.The circuit of the embodiment has a random number mode carry flip [1 block 60 is cleared, , the timing and control circuit 62 causes the entire circuit to operate as a periodic waveform generating circuit. (First startup) As shown in FIG. The knob 64 is cleared and the memory contents at ・ are set to O. Following this, from the 558th sound boat of RAM 50, as indicated by the arrows ■ and ■, the lower frequency data is first stored. I''O and the output signal B0 are read out and latched into latch circuits 66 and 68, respectively.
Here, the multiplexer 70 selects the waveform limber mask circuit 72 side. At this point, the waveform number mask circuit 72 is in the state of passing through the data. Therefore, addition: (The IC data EO and BO stored in the latch circuits 66 and 68 are supplied to the circuit 52, and the accumulated value Y
=FO+-804-CY is calculated. In addition, in this calculation of the highest position data, since cy=o, the output of the q adder 52 becomes Y-FO-IBO. 1 Upon completion of this calculation, a write pulse is supplied from the timing and control circuit 62 to the RAM 50 at 11 o'clock, and at 1^1 o'clock, the 3-state buffer 14 hears the write pulse, and as shown by the arrow ■, the write pulse is supplied to the RAM 50. Calculation data Y-F O-1-B
According to Figure 5 A in Olfi RAM, the sound boat's 801 entry area, i.e., the core mail area)
The data is stored in the memory 46. In this way, first, the base value BO on the tenth-best I side is updated and stored to the new cumulative Ω value. At this time, if a precision occurs due to the calculation of F・O+-B O and 1=, then 11'' is obtained, but if it does not occur, rot
However, as shown by the arrow ■, there is a digit toe-in 4. ;, CY
As a carry flip 70 from the CO terminal of the adder 52
It is held by a knob 64. (Second step) When the operations for - and series are completed, next step 1 and [
31 calculation, that is, the calculation of the second schedule is started. This operation C) is similar to the calculation in the first step, by reading out Fl and B1 from the soundboard of the RAM 50 (not shown in FIG.
, B, and at the same time, the carry flip knob is connected to the CI input terminal of the nasal ailator 52 via the multiplexer 76.
A calculation is performed that takes into account the carry signal CY held in one block, and the calculated data Y = F 14-81-I CY is stored as new data in the data B1 storage area of the sound boat and in the Zunawara Yuren memory 46. Stored in memory as . Also, at the same time, the contents of the 1 block 64 are also updated. (Third step) When the second step is completed, the calculation of the third step is started at vfl as shown in FIG. In this performance 9, as shown by arrows ■ and ■, RAM50
The process is started by reading data 2 and S from the 558th voice port and latching them into the latch circuit 66, and then shipping the data B2 into the latch circuit 68. At this time, the waveform number mask circuit 72 adds l' OJ as bit 5 to the lower 4 pits corresponding to F2 stored in the latch circuit 66, expands the data I-2 to 5 pits, and converts the data I-2 to 5 pits. 52. And, 52nd police officer, in this way, the latch circuit 6
6. Accumulate De Tato 2 and B2 supplied from 68,
As indicated by the arrow ■ (, that! 4! Value Y = F 2-
1-82-)-CY wo Same as above 1. : New data is written and stored in the storage area 82 of the board in FIG. 5A in the RAM 50, that is, in the final memory 46. At this time, in the third step calculation, the carry knob is 7.
Although the 0 knob 64 is not updated, the Killer flip knob 64 still holds the CY in the second step, so it is cleared as an arbitrary value at the beginning of the next sampling operation. (Fourth step) When the main operation consisting of the first to third steps is completed, the waveform data stored in the waveform memory 40 is read out as shown in FIG. 8. That is, the operation of the third step is performed. At the time of termination,
From addition 'a52, output value data after addition (Y=F2+
At the same time, the waveform number S is outputted from the latch circuit 66 as shown by the arrow ``2'', and is supplied to the waveform address 40 as a summing address. When the output data Y and the waveform number S are supplied to the waveform memory in this way, the waveform memory 4
The waveform data stored in 0 is outputted to the waveform latch 54. Further, in conjunction with the sampling readout operation of a series of waveform data, the gain Go is read out from the sound boat shown in FIG. 5A of the RAM 50, and the readout data is (The direction is supplied to the waveform latch 54. The waveform data latched in the waveform latch b4 in this way and the gain Go are
A-] is converted into an analog signal in the converter 56, and is simultaneously converted into an analog signal and output until the time when waveform reading for the next sampling operation is started. Then, by repeating the sampling operation consisting of the first to fourth steps as many times as given by the equation (1) above, one cycle of the arbitrary periodic waveform selected by the waveform number -8 is read out. Output. In this way, in the circuit of the embodiment, the first to
By repeating the operations of the fourth step for each dial, it is possible to read and output the Ic cycle waveform stored in the waveform memory 50 with a desired read cycle and gain Go. In addition, when obtaining a subareo effect, prepare another set of the waveform latch 54 and the DA latch 56, and read the gain G1 from the sound boat not shown in FIG. 5A in the RAM 50 as described above. By outputting J, this gain G1
It is also possible to read out a predetermined periodic waveform whose amplitude is determined by . In addition, in the circuit of the embodiment, each time the series of sampling operations of the first to fourth steps described above are completed, the data N read from the sound boat shown in FIG. The data N read in the mode detection knob knob 60 in this way is the next chip 1? The operation of the channel is determined to be periodic waveform generation operation or noise waveform generation operation described below. In this way, the circuit of the embodiment is shown in FIG. 13, for example.
In FIG. 14, any periodic waveform can be generated at a desired period. This is the periodic waveform generation operation in the circuit of this embodiment.Next, the noise waveform generation operation performed using the circuit of this embodiment will be explained. (C-2) Noise waveform generation operation In the 1st 1st path of the embodiment, 5'IL g waveform generation! [The operation is such that the output of the random number mode detection flywheel knob 60 is 1.
Thus, when the output of the knob 60 becomes 1, the timing and control circuit 62 controls the entire circuit to be dynamic for noise waveform generation. When the noise waveform generation operation is started in this way, the circuit tit of the embodiment first starts with shift permission (,
2) A random number generating unit that generates random numbers based on the shift pulse generator 41 that outputs the shift pulse generator 41 for outputting the shift pulse generator 41 for outputting the shift pulse generator 41 for outputting the shift pulse generator 41 for outputting the shift pulse generator 2) Perform the action as the fourth sura. A random number generated as a whirlpool causes a miscellaneous γ7 Buddhist name! 1
Take action to do so. Each of these operations will be explained below in order of snop. . (First step) At the same time as the 51γl waveform generation/1iFIJ operation starts, the circuit of the embodiment operates as a shift pulse generator 20, as shown in FIG. However, the circuit of the embodiment starts operation and ri'ij II
Clear the key VR flip 7O knob 64 as indicated by the arrow 1 and start reading the data from the random number generation soundboard shown in FIG. 5B of the RAM 50 for 1 m. To read this data, as shown by arrows ■ and ■, frequency data F and accumulated data B are read out from each memory 24 and 26 of the sound boat shown on the 55th page, and latch circuits 66 and 68, respectively.
flag within. The data F and [3 latched in the latch circuits 66 and 68 in this way are transmitted to the trunk unit 52, and Y.
・Output as the value of Fl-8. Then, JY-F+8 obtained in this way is stored as the new accumulated value data B as the accumulated value f-ta B shown in Soundboard 1-FIG. L/, that is, i'J is stored in the cumulative memory 26. This old loading operation is performed as shown in 1 below. First, the calculation operation for data F-1B is performed. 1 [As a result, when the addition value of the addition lr [device 52 is A- part low, the addition τ> is sent from the CO terminal of the device 52 to the random number 1-t series -Noritsub) 1] Supply to the 776, and this will enable you to use random numbers? The Lee flip-flop 7G outputs to the timing and control circuit 62 the signal W-11, which corresponds to 1 from the bell-circuit 28 in the 34th B; Next, the timing and control circuit 62 outputs a write-in pulse WP to the RAM 50, and the cumulative value data is updated. Hereinafter, the second and subsequent steps will be explained assuming that shift permission (No. 5) has been output. (Second step) In this way, the random number keys are set to 20.
When the jit permission signal P is output from the step 76, the timing and control circuit 62 controls the entire circuit as a random number generator as shown in FIG. In this way, the circuit of the embodiment is controlled as a random number generator, but as shown by the arrow ■ in the figure, the memory that functions as the random number memory 34 in the random number generation soundboard shown in the 54th B of the RAM 50 The random number $1ma0 on the 1st digit side is read out from the area and sitched into the latch circuit 68. At this time, the multiplexer 70 selects the latch circuit 68 side, and therefore, as shown by the arrow ■1, the multiplexer b2
The data 80 sitched to the latch circuit 68 is supplied to both terminals of the latch circuit 68 . At the same time as this operation, the multiplexer 71 switches to the feedback value memory 78 side, and as shown by the arrow ■, the feedback value read from the feedback value memory 78 becomes 1=1 of the adder 52.
11 is input to the input terminal CI. The feedback value memory 78 is an addressable memory having a capacity of 16 equal to the number of channels, and in this embodiment is configured as a (1 bit)×16 RAM. Also, the feedback value written and stored in this IM return value memory 18 is the same as that of the feedback circuit 12 during the previous random number generation operation.
This is serial data input via . As a result, from the adder 52, Y-2XS110(-(
The value of the feedback value) is output, and this value is stored in the fifth memory of the RAM 50.
Shown in 4B! jsRo data 1 rear (random value memory 34)
is written and stored as new data. . Then, at the same time as inputting such data, the adder 52G inputs a digit from the co terminal to the 8-bit 1 (C number cy
= Carry flip-flop 6 as shown by arrow ■ for i
Supply to 4. In this way, the update of the data SRO on the -to side is completed.
Then, updating of the second-place data SRI is started. This operation is performed as shown in the jj<1>. (Third Step) First, data 5rti on the 1st position is read out from the random number generation sound port shown in No. 54B of the RAM 50 as indicated by the number L and the arrow ■, and is latched into the ship circuit 68. At the same time, the waveform number does not appear from the new boat as indicated by the arrow ■, and the data S lfi 1. The output signal is extracted and latched into the latch circuit 66. When this latch operation is completed, the lublexer 70 has selected the latch circuit 68 side, so next, as shown by the arrow
is supplied to both ends f of the adder 52, and at the same time the digit 1 signal jI3 CY held in the carry node 64 via the multiplex () 71 indicated by the arrow ■ is supplied to the adder 52. is supplied to the sharp input terminal CI. As a result, the processor 52 outputs the value Y = 2
As shown by the arrow ■, S shown by the 54th B in the RAM 50
The data is written and stored as new data in the R1 data storage area (random value memory 34). In this way, a new random number is randomly stored in the sound board sr<o for recording random numbers and the SRI memory 1 rear (random number value field 34) shown in the 54th B. Two and one = become. . Also, from Kakai 1552, decoration data Y=2XSR1toC
When Y is output, the feedback circuit 12 stores the feedback value in the next random number generation operation in the feedback value memory 7 as indicated by the arrow ■.
Write and store in 8. (Fourth Sugetsubu) In this way, when a new random number is inherited and stored in the sound boat shown in FIG. It functions as a circuit for CI. However, at the end of the third step, the waveform number S is latched in the footge circuit 66, and the waveform number S is indicated by the arrow .
0. At the same time, the adder 52 outputs the calculation result Y-2 It is supplied to a waveform meter 40 as a recombinant signal which determines the demultiplexing effect. As a result, the waveform data is read out from the waveform memory 40 and latched into the waveform latch 54 as indicated by the arrow ■. At the same time as reading out such waveform data, in the circuit of the embodiment, data Go that determines the amplitude is read out from the sound board as indicated by the arrow ■, and the data Go is read out from the waveform latch 5
latched within 4. When the waveform data and gain are latched in the waveform shoe 1 in this way, the trace is as shown by the arrow ■.
The data is supplied to the DAj converter 56, where each data is multiplied and simultaneously output as an analog random number waveform signal. In this way, the circuit of the embodiment randomly samples and outputs the waveform difference of the selected waveform as a read noise waveform signal based on the random number provided. Note that in the circuit of the embodiment, the waveform latch 54 and the DA
By providing an additional pair of two inverters 56, a fifth
As shown in FIG. B, it is also possible to read out the gain G1 of the sound boat and output a noise waveform based on this gain G1. Then, after outputting the waveform of the noise signal such as ξ-, the T-ta N is read out from the round bottom in Figure 5B as shown by the arrow ■, and the next dial operation is performed. stipulate. . The predetermined random waveform data consisting of the first to fourth slaps are all assembled and read out by the
) in formula 1. By repeating this process for the number of times t-J<Jλ, the waveform data of the periodic waveform selected by the waveform number S is output for one period as a noise waveform. Next, an example of the arbitrary Brennnel Miuhata waveform using (1!) the 1Iij path of the example/! ! :Explanation. First, it is assumed that the sound boat shown in Fig. 5, 8k'' of the arbitrary button channel is J3 at the start of the simple!l1lj operation, and the contents of Fig. 5C are 4:Jσ.In this case, the frequency data F is 10 Since F=・11 in decimal notation, the carry of cumulative data B is the number of updates (recycle) of D-8.
The back of 256 times 77 rrn occurs. At this time, this sampling frequency F is determined according to equation (4), which will be described later, as follows: r = 93.75 F = 7218.7b L HZ
Table 3 shows the compression data of each sleeve of J3 during one movement of the shoulder 1 waveform of this embodiment, and iX 1 - Based on this compression data, the embodiment The sampling process will be carefully examined. Here, as is clear from FIG.
, each waveform data of the waveform selected by the waveform number 5=6 (hexadecimal number) is stored at its physical address OCO
~ Corresponding to OCF, it is 1i1+, and the waveform data of this area is as shown in Table 4. First, as described in detail in the first step, when the circuit of the embodiment operates as the shift pulse generator 20, the value of the cumulative data B becomes "= 0100110" as shown below.
It is updated one by one (binary number). (Main number of days) 1st
0100.1101÷0110,1001 =1011
．． 0110 Umbrella 2 times f:I 0100.1
101 + 1oi 1.0110=OOOO,00
113 times U40100.1101÷0000.0110
．． =0101.00004th time 0100,110
1) 01G1.0000=1001.11015rO
J100 〇100.1101 +1001.110
1=1110.1010$6th 0100,11
01)1110.1010=0011,01117 times 0100,1101,)0011,0111
=1000.01008 times ()100.110
141000.0100=1101.0001 9th mouth 0100,110141101.0001=00
01,11101011010 times 0,1101 +0
001,1110=0110,10111101111
110140110.1011=1011.10
001200012 times, 110141011.100
0=OOOO, 0101 In this way, when the circuit of the embodiment performs the update operation of the cumulative Ei5'-taB as the shift pulse generator 20, the decorator 32 (the emitter 28 in FIG. 1)
is the 2nd cycle, the 6th cycle, the 12th cycle...
・Over--C1- shift permission signal j! P-
1, and the circuit generates a random number f! once every 3 or 4 cycles. Make it function as $22. In Table 3, SHn excludes the cycle in which the circuit functions as the random number generator 22. , as is clear from Table 3, the circuit number of the embodiment is N2. N6, N9. NG・
...Acts as a random number generator in the cycle. When the circuit functions as the random number generator 22 in this way, the feedback value is read out from the feedback value maker 78, as described in detail in the second slap, and the feedback value is read out from the feedback value generator 78.
In the circuit shown in the figure, the signal is input to the key 11 input terminal CI of the booster 36). This feedback value was set based on the following logical formula when the random number was generated last time, [Feedback value] - ([Bit 15] 113 [Bit 13
] ) (1) ([Bit 121Φ [Bit 10]) (However, AωB represents 1 scrou shibuo/ of A and [3.) In the embodiment, for example, when a random number is generated for the first time, the feedback value is (0■1)e(OΦ1)=1, and when a random number is generated for the second time, its feedback value becomes (1ΦO)■(OG)O)-0. The feedback value column of Table 3 shows the feedback values obtained in this way. The example circuit is shown in the previous &! As described in detail in the second and third steps, each time it functions as the random number light A1 unit 22, it outputs a random number as shown below using the 9i+) far 1G, and outputs a random number as shown below. In other words, the random numbers in the sound boat St"(1, SR2 memory and L rear as shown in FIG.
11.01001st time 1100.101
1.0110.10012 times 1001
．． 0?10.1101.00103 times
0010.1101.1010.01004 times
0101.1011.0100.10015 times 1011.0110.1001.00
106th session 0110.1101.001
0.01017 times i1o+, 1oi
o, oioo, 1o1i 8th time 10
11.0100.1001.01119 times
0110.1001.0010.11111011
110 times 1101.0010.0101.1110
1111011 times 1010.0100.1011.
1101121! In 0100. 1
001.0111. 1.01013 times
tooi, ooio, 1i11. oio114th ooio, oiol, mo, 1o
ii15th 0100.1011.1'1
01.01111611116 times 1001.011
1.1010.1111 The random number column of Table 3 shows the random numbers updated in this way. Each time a random number is output in this way, the circuit of the embodiment stores bits 8 to 12 of the updated random number in the waveform memory 40, as described in detail in the fourth block J3. Waveform data ()°Used as sampling address. In this way, the number of random numbers updated in hexadecimal numbers is as follows. 08, 16.00. 1B, 16.00. IA
, 1409, 12.04.04.12.05.0B
, 17 Here, the waveform boomer specified by the sound boat not shown in Figure 5C is S -0110 (2
speed number) = 6 (hexadecimal vl), therefore, considering the waveform number S, the address manually entered in the waveform memory 40 is the following 9-bit j, 4I, etc.
Ru. OCB, 00(i, OCD, 00B, ODG, OCD,
0 mouth^, 0040C9,0112,0(:4.009.
0f)2. QC! +, OCB, 00'/The address shown above is shown! , two-period waveform light t, , +1;'i is a random address unlike the address of i, so the waveform data selected by waveform number S-6 shown in Table 4 is read out randomly by the address. 85 shows the waveform data read out randomly in this embodiment, and this value is set as gain GO=
1010A multiplied by I), it is possible to sample and output the noise waveform data used to obtain the waveform latch output in Table 5. FIG. 15 shows the noise waveforms sampled and output in this way, and as is clear from the figure, according to the circuit of the embodiment, the waveform selected by the waveform number S is By randomly sampling and reading the waveform data, it is possible to output a desired noise waveform. In addition, in this embodiment, the case where the feedback value memory 78 is used when the circuit operates as a random number generation α section has been explained as an example, but the present invention is not limited to this.
9 without using direct memory 78! +) Inputting the output of the far circuit 12 as it is to the adder 12 also results in poor performance. As explained above, according to the circuit of this embodiment, when the periodic waveform generation circuit and the noise waveform generation circuit are combined, the main parts of the circuit, such as the decorator 52) and the waveform generator 40, are shared. As a result, it is possible to increase the degree of integration of the entire circuit and reduce costs. (C-3) Examination of data Next, we will examine specific data when the circuit of the embodiment is used as a periodic waveform generating circuit and a noise waveform generating circuit. . (a) Frequency of periodic waveform First, check the specific readout frequency of the periodic waveform that is 1 by the circuit of the embodiment. (Limbbling period of channel) The circuit of the embodiment is (The data in AM50 is accessed on the hour and minute side in synchronization with CP (Novus 1Nikle I'ec, and as mentioned in flit, the sampling period per channel is CI) 4 periods of U bus cycle minutes, so the sampling period per channel is 4/foe. In the embodiment, as mentioned above, there are 16 channels, so the sampling period of each channel G; L16X
(4/I' B C). (Number of samplings per waveform) Also, when considering the number of sampling operations performed to read out one waveform, the core data 46 has 21 bits, and the cumulative value of data B is 21 bits. The accumulated value 13 in the waveform memory 46 increases by F.
produces A゛- part 1 cor, and then the next A- part ``
1-, that is, the number of samplings N performed in the dark when the waveform is read out is 2"/do. (Period of the output waveform) Therefore, the above sampling period and the In By multiplying by the number of times, the period 1/" of the output waveform can be found as follows, It becomes "-□...(3) 16X 4X2". In this embodiment, since the CPU bus cycle frequency foe is rec -1,536 MHz, the frequency of the output waveform is r SO,011444-F (+12). Follow two (, f = 440 (llz) (1) Output'
151NI (A
), it is sufficient to set the frequency data = 38448 within one round port. Consider the frequency t.The random number sampling output is an 8-pit simple memo 926
Since the simbling frequency is performed every time there is an overflow, the simbling frequency can be obtained by the following equation in the same way as the equation (3) above. fuc-F f = −-24・fuc-F16X4
X26 =93. '15 ・fL [11z] φ
φ-(4) Therefore, in order to obtain a sampling frequency of 3[to 11Z], it is sufficient to set the frequency data of r=-32 in the sound board according to FIG. 5(B). Next, regarding the random number generation period GORND of each block [
Examination, IRNol, Leanbring period 1/f
2-1 = 65535-8, which is given by the following formula. 2"-12' -rRN D-
It is understood that the time is 21,845 [seconds]. "Effects of the Invention" As explained below, according to the present invention, by using a time-sharing method, the number of circuit components can be reduced, and as a result, the ttaa of the entire circuit can be increased and random number generation can be performed at low cost. It is possible to provide a circuit. Table 1 Contents of waveform memory 4 5

[Brief explanation of the drawing]

Figure 1 shows the origin of the random number generation circuit used in the present invention (・2)!
l! Explanatory diagram, Figure 2 is a diagram of the conventional random number generation circuit, Figure 3A
Figure 3 is a principle diagram of an L-period waveform light circuit, Figure 3 is a diagram of a miscellaneous waveform generation circuit, and Figure 4 is a diagram showing a preferred embodiment of the present invention. The diagram is shown in Figure 4! An explanatory diagram of the periodic waveform generation soundboard 1- and the random number generation soundboard stored in the JRAM, see Figure 6. Figure 8 is shown in Figure 1, and the circuit operates as a periodic waveform generation circuit. An explanatory diagram of the case shown in Fig. 9. Fig. 12 is a diagram of the circuit not shown in Fig. 4, which is generated by noise. FIG. 12... Feedback circuit 20... Shift pulse output section 22... Random LU section 32... Shift circuit 40... Waveform memory

Claims (3)

[Claims] (1) An accumulation memory for storing accumulated values, and a memory for adding the accumulated value and externally inputted frequency data and writing and storing this added value as a new accumulated value in the accumulation memory. 1 adder, and a shift pulse output unit that outputs a shift pulse based on a carry signal generated when the cumulative value of the first adder overflows; and a random value memory and a second adder, a shift circuit that functions as a shift register by adding multiples of the random value memory contents using a second adder to update the contents of the random value memory each time a shift pulse is input;
a feedback circuit that feeds back a feedback signal to the carry input terminal of the adder, and a random number generation unit that generates a predetermined random number in the random number memory, the first adder and the second adder. The random number generation circuit is characterized in that the same adder is shared in time division. (2) A random number generation circuit according to claim (1), wherein the accumulation memory and the random number memory are formed in different addresses of the same memory. (3) In the circuit according to any one of claims (1) and (2), the shift pulse output section includes a timing generation circuit that generates a predetermined timing signal, and the timing signal and
A random number generation circuit characterized in that an AND output with a carry signal output from the first adder is output as a shift pulse.