JPS6146473Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic wristwatch, and more particularly to an improvement in a drive circuit for a pulse motor, which is an electromechanical conversion mechanism thereof.

Since the so-called quartz wristwatch, which uses a quartz oscillator as a time standard oscillator, was put into practical use, numerous technological innovations and improvements have gradually increased production volume and lowered prices, leading to the widespread use of quartz wristwatches today. However, in analog quartz wristwatches with pointer displays, technological innovations related to crystal oscillators and electronic circuits have been remarkable, but compared to this, electromechanical conversion mechanisms have lagged behind. In other words, from a cost standpoint, this component plays a large role among the components of a quartz wristwatch, and from a performance standpoint, most of the power consumption is consumed by this electromechanical conversion mechanism, which increases the lifespan of the quartz wristwatch or increases battery life. Due to miniaturization, watch bodies are becoming smaller and thinner, which is becoming a major problem.

In order to improve the above-mentioned drawbacks, the present invention adopts a two-pole rotor type pulse motor as an electromechanical conversion mechanism, and by optimizing the shape of the motor, it eliminates the need for adjustment of the pulse motor and reduces costs. By adopting a drive system suitable for the motor, stable operation is possible with low power.Examples will be explained in detail below with reference to the drawings.

FIG. 1 shows an example of a pulse motor according to the present invention.

In Fig. 1, reference numeral 1 denotes a rotor made of a permanent magnet magnetized into two poles, and stators 2 and 3 are arranged facing each other with this rotor 1 in between.These stators 2 and 3 each have a coil. 4 is connected to a wound yoke 5 to form a set of stators. The stators 2 and 3 have their arcuate portions 2a and 3a eccentric by X with respect to the center of the rotor 1 so that the rotor 1 can rotate in a fixed direction.
The magnetic pole (N and S) positions of the rotor 1 when it is at rest are shifted to one of the stators 2 and 3. This type of pulse motor has been in practical use for some time and was driven by a circuit block as shown in FIG.
Reference numeral 10 denotes a crystal oscillator, which is driven by an oscillation circuit 11, whose frequency is divided by a frequency divider 12, and a waveform shaper 13 which generates two pulses having an appropriate time width and a 180° phase difference at an appropriate time interval. is formed.

As an example, we will consider a pulse of 7.8 m sec every 2" and explain this below.
Driver 1 consisting of CMOS inverter
4 and 15, and the output is sent to terminal 4 of coil 4.
a, 4b. FIG. 3 is a detailed diagram of this driver section. When a signal 18 is applied to the input terminal 16 of one inverter 14, a current flows as indicated by an arrow 19, and conversely, a current flows to the input terminal 16 of one inverter 14.
When a similar signal is applied to the input terminal 17 of 5, a current flows in a route symmetrical to arrow 19. That is, by applying signals alternately to the input terminals 16 and 17 of both inverters, the current flowing through the coil 4 can be alternately reversed. Specifically, a current of 7.8 m sec that is alternately reversed every second can be reversed. It can be passed through the coil 4. With such a drive circuit, N is applied to the stators 2 and 3 of the step motor shown in Figure 1.
Pole and S pole are generated alternately, and the rotor 7 can be rotated 180 degrees by repulsion and attraction with the magnetic pole of the rotor 1. The rotation of the rotor 1 is transmitted to the fourth wheel 6 via the intermediate wheel 6, and then to the third wheel 6.
The signal is transmitted to the pinion wheel 8, the second wheel 9, and further to the cylinder pinion, hour wheel, and calendar mechanism (not shown), and operates an indicating mechanism consisting of a clock, minute hand, second hand, calendar, etc.

The pulse motor shown in FIG. 1 operates in principle as explained above, and has been used as a conversion mechanism for electronic wristwatches.

The present invention aims at extremely low power consumption of this pulse motor using the drive method described below, and will be described in detail below.

In the drive circuit shown in FIG. 5, a high level signal is applied to the terminal 17, a signal 18 is applied to the terminal 16, and the arrow 19
When a current flows as shown in MOS transistor 1
5, a voltage drop based on the drive current occurs due to the channel impedance, and a signal corresponding to this current can be detected at the terminal 4b. The current waveform is, for example, a waveform 20 shown by a solid line in FIG. As is clear from the figure, the major feature of this current waveform 20 is that there is a part (indentation) where the current value decreases in the middle, and the reason why the current changes rapidly is due to the voltage applied by the drive circuit. This is because an induced current is superimposed on the coil due to the rotation of the driven rotor, in addition to the current generated by the rotor, and the dent in the current waveform is the part where this induced current is maximum. This corresponds approximately to the time when the magnetic field change within the range is maximum, that is, when the magnetic pole of the rotor passes through the gap (δ ₁ , δ ₂ part) between both stators.

The above is the operation of the pulse motor in a no-load state, but when a load is applied to the motor, the current waveform changes. This state is a waveform 21 shown by a dotted line in FIG. 4, and further a waveform 22. Among these, waveform 22 shows an example of a current waveform under a critical load state, and the rotor cannot complete rotation under a load greater than this. When considering the characteristics of the rotor rotation and drive current waveform, the above 2.
There is a clear correlation between the two operating characteristics. Under no-load conditions, the motor completes rotor rotation when the current flows to a point where the current waveform reaches a dent, that is, the rotor's magnetic poles pass through the stator gap. Alternatively, rotation may be completed even if the current is cut off well before the waveform depression. As the load increases, the critical point at which the rotor completes its rotation will shift somewhat further back on the current waveform than in the no-load state. This is because the mechanical critical angle of the rotor that completes its rotation with respect to the stator is somewhat larger than when it is under no load. Additionally, the dent in the current waveform shifts backward as the load increases, indicating that the rotor starts to rotate more slowly. The no-load state described here,
Specifically, the load state refers to a case where the load applied to the motor changes due to, for example, a calendar mechanism such as a date wheel or a day wheel being in an inactive state or in an active state. Due to the above facts, the sufficient pulse width of the drive signal to be applied to the motor varies depending on the size of the load and is not constant. In addition, in the case of a pulse motor whose motor structure, coil, core, and other constants are constant, the current waveform under each load condition and the pulse width necessary and sufficient to complete the rotation of the rotor at that time are almost unique. Therefore, for motors of the same model, it is possible to match the required pulse width points on the current waveform on a one-to-one basis in each load state. In Figure 4, waveform 20 under load
Although it has a margin when a load is applied, a large amount of wasted current flows when there is no load, so the pulse width of 7.8 m sec is set to the pulse width at maximum load. I understand.

The drive system of the present invention focuses on this drawback, and detects the rotational state of the rotor from the waveform of the motor drive current, regardless of whether it is under no load or under load, and cuts off the drive current that exceeds the necessary level, thereby reducing the load size. The driving pulse width is changed accordingly, so that the driving circuit is always driven with the lowest power consumption. An example of the driving circuit is shown in FIG. 5, and a time chart thereof is shown in FIG. 6. Terminals 23 and 24 correspond to terminals 16 and 17 in the conventional circuit diagram of FIG. 2, and apply signals A and B in FIG. 6. That is, crystal resonator 10, oscillation circuit 1
1, the frequency divider 12 and the waveform shaping circuit 13 are similarly used in the present invention. That is, although the phases differ by 180 degrees, a pulse of 7.8 m sec is applied every 2 seconds. The output of terminal 23 now changes from HIGH to LOW as shown in the first pulse of FIG. 6D. the other
Since the output of the NAND gate 26 is HIGH, a current flows in the coil 4 from the terminal 4a to 4b, and as mentioned above, an internal voltage drop based on the drive current occurs due to the channel impedance of the MOS transistor, and the sixth The waveform of the current flowing through the coil is observed as shown in the first pulse of Figure C. That is,
NAND gates 25 and 26 constitute a gate circuit 100 that supplies current to the coil. This current waveform is alternately selected between terminals 4a and 4b by analog switches 27 and 28 constituted by transmission gates, and is amplified by an amplifier 29. amplifier 2
The input signal and output signal of 9 are shown in Fig. 6 E and F, respectively.
Shown below.

Reference numeral 101 in FIG. 5 is a rotor position detection circuit, and each component will be explained below. Reference numeral 30 denotes a delay circuit which samples the output signal of the amplifier 29 and delays it by a time preset by a clock 33. Reference numeral 31 is a comparator circuit which receives the output of the amplifier 29 and the output of the delay circuit 30, and determines whether the two input signal levels are high or low to generate a HIGH or LOW output, and is composed of a differential amplifier or the like. As mentioned above, 32 is a judgment circuit that cuts off the width of unnecessary motor drive pulses using the time reference 34 based on the output of the comparator 31 which changes according to load fluctuations. Incidentally, as shown by H, the output of the judgment circuit 32 rises in synchronization with the application of the drive pulse A, and the NAND gates 25 and 26
Open state, detect the concave position of the current waveform C or E by the output of the comparator circuit 31 (the rotor circuit rotation is completed if the current is applied up to this point), and raise the output of the judgment circuit 32 to make the NAND By cutting off the gates 25 and 26, the minimum necessary drive current is supplied. Note that the clock 34 and the output signal 5 of the comparator circuit 31 shown in FIG.
The circuit for forming the output signal of FIG. 6H from the two signals of FIG. .

As described above, the amplifier 29, delay circuit 30, comparator 31, and judgment circuit 32 constitute the rotor position detection circuit. The delay circuit 30 uses a bucket brigade type charge transfer element, which will be described later. In FIG. 3, the channel impedance of the driving MOS transistors 14 and 15 is set to about several tens of ohms in consideration of efficiency from the power supply voltage (1.3 to 1.8 V) and the resistance of the motor coil (2K to 5K). At this time, the current flowing through the coil is several hundred μA at most, and therefore the voltage drop based on the channel impedance of the transistor, that is, the amplitude of the detected current waveform is from several mV to about 20 to 30 mV at most. 7th
The figure shows an example in which the amplifier 29 is constructed of CMOS. Reference numerals 35 and 36 are analog switches, that is, transmission gates corresponding to 27 and 28 in FIG. Do it as you like. At this time, the output terminals of switches 35 and 36 are connected to each other and are at the same potential as the selected point of 4a or 4b, and the value is determined from the above explanation, assuming that the positive power supply potential of the circuit is +V. , +V - becomes several 10mV. 37 is an AC coupling capacitor for transferring the potential of the detection signal to the input operating potential of the downstream amplifier;
Together with the load resistance in the subsequent stage, the capacitance value is such that a sufficiently large time constant compared to the signal frequency can be obtained. 39 and 40 are P channel and N channel
It is a MOSFET whose control gates and drains are connected to each other, and negative feedback is applied from the output terminal to the input terminal through a resistor. This constitutes a CMOS amplifier. The gain of the amplifier is approximately 20 dB to 30 dB, as long as it provides an input signal to the subsequent comparator that allows the comparator to operate sufficiently faster than the pulse control time. FIGS. 8 and 9 are examples of circuits that shift the voltage level without using the AC coupling capacitance 37. 42, 43
is a resistor connected in series and is a voltage dividing resistor whose value is set so that the potential at the connection point is equal to the standby state potential of the amplifier. Further, the resistance values of 42 and 43 are selected to be sufficiently smaller than the feedback resistor 38. Figure 9 is the 8th
This is an example of a circuit that has been further improved from the diagram. 44 is a circuit that detects whether the output level of the amplifier in the standby state is close to the original standby level, and if the output level deviates significantly from the standby level. , the waiting level of the input point is controlled to move up and down through the negative feedback transistor 45. FIG. 10 shows a general example of the delay circuit 30. 46 and 47 are connected in series
It is a bidirectional analog switch or transmission gate with CMOS structure. The number of stages of transmission gates can be further increased if necessary, and the number of stages is set according to the delay conditions. Capacitive loads 48 and 49 are coupled to the output terminal of each transmission gate for storing charge corresponding to an analog signal. The transmission gates 46 and 47 sequentially repeat switching according to the delay conditions, delaying the analog signal supplied to the input terminal 41 for a certain period of time, and outputting the delayed analog signal to the output terminal 50. However, in the case of a capacitor, the charge transfer loss is large, so in the present invention, an analog data shift register composed of a bucket brigade type charge transfer element is used, which is shown in FIG. In FIG. 14, electrodes a, b, c, and d correspond to each stage of the shift register, and each electrode is connected to every other stage, and clock pulses φ ₁ and φ ₂ are applied, respectively. g is an oxide film insulating the semiconductor layer f from the electrodes a, b, c, and d, and e is a so-called P-type bucket arranged asymmetrically with respect to the electrodes, as shown in the figure. At this time, the semiconductor layer f is made of an n-type semiconductor. FIG. 15 shows the energy level of each register in the accumulation mode and the charge accumulation state in each bucket corresponding to the analog signal. 1st
FIG. 6 shows the energy level and charge transfer situation in the data transfer mode. In the state shown in FIG. 3, by applying a lower voltage to electrode b, the energy level of the bucket under electrode b is lowered than that of the adjacent bucket part. It can be seen that by alternately applying voltage pulses to φ ₁ and φ ₂ , the accumulated information in the bucket is sequentially shifted. MOS at the end
A type FET or other voltage detector is connected to couple the shift register with the subsequent analog circuit. Therefore, when using a shift register composed of this bucket brigade type charge transfer element in the circuit shown in FIG. 5, the output of the amplifier is connected to electrode a of the shift register shown in FIG. As the output of the register, comparator 31
connected to. At this time, as described above, a MOS type FET or the like is provided at the end of the shift register in order to match the levels. FIG. 11 shows a time chart of these signals, where 51 is the input signal waveform supplied to the terminal 41, and 52 is the delayed signal outputted to the terminal 50. FIG. 12 shows waveforms that are further modeled. 54 is the waveform that appears at the terminal of the capacitive load 48, and 52 is the waveform that appears at the output terminal 50. The result is a sampled step-like waveform. The comparator 31 compares the levels of the outputs of the amplifier 29 and the delay circuit 30, that is, the waveforms 51 and 52 in FIG.
Outputs LOW level output. The waveform is shown in FIG. 1153. It is clear from FIG. 11 that the level inversion position of the comparator output signal corresponds to the point indicating the peak or extreme value of the motor drive current 51. For pulse motors of the same standard, the drive current waveform for each load state and the rotation critical point on the current waveform (minimum pulse position for the motor to complete rotation) are uniquely determined, so the comparator 31 By knowing the output of the waveform 53, that is, the rising or falling position of the waveform 53, the necessary pulse width for each load can be determined. Alternatively, by detecting fluctuations in the rising and falling positions of the waveform 53 with reference to the clock signal, it is possible to set the required minimum pulse width at each load. Block 32 represents such a control circuit, and terminal 34 is a time reference signal. FIG. 13 shows an example of a pulse motor drive current waveform by the electronic timepiece according to the present invention. In the figure, 54 is the current waveform in the no-load state, 55 and 56 are the current waveforms in the loaded state, and 56 is the current waveform when the load is further increased than 55. The broken line is an imaginary diagram of the current waveform without pulse width control. Note that CMOS amplifier 2
9 and the comparator 31 are configured together with a clocked gate or an inhibit gate, and can be configured to operate only when the pulse motor is driven, thereby cutting unnecessary current. As mentioned above, the present invention aims to reduce power consumption by cutting off unnecessary current when driving a pulse motor, and also requires other special mechanical means to detect the current flowing to the motor. In addition, the amplifier in the control circuit is also constructed of CMOS, and the control circuit is streamlined and has low power so that the amplifier operates only when necessary.

As described above, the present invention aims to optimize the drive of the pulse motor and realize a low-cost, stable electromechanical conversion mechanism with low power consumption, thereby making it possible to reduce the cost, extend the lifespan, or downsize electronic wristwatches. . In particular, according to the present invention, the induced waveform generated in the coil when a drive current is applied is amplified, and the amplified output and the delayed output signal passed through the delay circuit are used as inputs of a comparator to detect the rotor position.
Since a bucket brigade type charge transfer element is used in the delay circuit, accurate rotor position detection without charge transfer loss is possible. Furthermore, since it can be integrated with other timepiece circuits, it has the advantage that the circuit can be easily handled during manufacturing and assembly.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a pulse motor and a wheel train according to the present invention. FIG. 2 is an electronic circuit block diagram of a conventional electronic timepiece. FIG. 3 is a detailed diagram of the drive circuit of FIG. 2. FIG. 4 is a current waveform diagram of FIG. 3. 5, 7 to 9, and 14 show one example of the circuit of the electronic timepiece according to the present invention, and FIGS. 6, 11 to 13, time charts and current waveform diagrams. It is. 15 and 16 show the potential distribution in FIG. 14. FIG. 10 is a circuit diagram showing a general example of a delay circuit.

Claims (1)

[Scope of utility model registration request] an oscillation circuit, a frequency divider that divides the output signal of the oscillation circuit, a waveform shaping circuit that outputs a pulse signal that forms a drive pulse based on the output signal of the frequency divider, and a drive circuit that operates based on the pulse signal. , an electronic timepiece comprising a stator, a rotor, and a pulse motor including a coil and driven by the drive circuit, wherein the drive circuit includes a gate circuit 100 that applies a drive pulse to the coil based on the pulse signal; The rotor position detection circuit 101 detects the rotor position from the induced current generated in the coil when the rotor is driven by the drive pulse, and the rotor position detection circuit 101 is connected to each of the terminal portions of the coil. Two analog switches 27 and 28 which are alternately controlled to be conductive by pulse signals, and a CMOS amplifier 29 connected to the analog switches.
and a delay circuit 30 consisting of a bucket brigade type charge transfer element that delays the output signal of the amplifier, and detects the rotor position from the displacement point of the output voltage by inputting the output signal of the amplifier and the output signal of the delay circuit. and a determination circuit 32 that outputs a signal to cut off the gate circuit when the comparator detects that the rotor has rotated by a predetermined angle.