JPS6146836B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for displaying characters, figures, etc. used in data terminals and the like.

In recent years, many data terminals have been designed to display characters, figures, etc. for the convenience of users. Such character display devices are becoming more and more capable of displaying large amounts of characters, becoming more sophisticated in their functions, and becoming faster at processing speed. When using buffer memory to display stored information on a cathode ray tube, data must be transferred for 40 to 60 screens per second, so reducing the processing time required for screen control is an important point. . Furthermore, as the information transmission speed of data communications increases and terminals become more intelligent, reducing processing time becomes even more important. Since the processing time related to screen control occupies a large proportion of the processing time of a character display device, it is very important to shorten the processing time related to screen control. On the other hand, character display devices in data terminals and the like are often required to have a screen vertical movement function (scroll up/down function) from the viewpoint of service functionality. Scroll up means to move the display screen shown on the left side of Figure 1 upwards one line at a time until it becomes the display screen shown on the right side of Figure 1. In some cases, the top line of the previous screen is displayed, as shown in , and in other cases, a completely new display is displayed. On the other hand, scrolling down means moving downward and performing the opposite operation to the above. In addition to this, a function to divide the display screen into a plurality of sections and display different information may be required. In this way, when displaying the screen in an order different from the storage order of the buffer memory, conventionally, for example, as shown in FIG. After rearranging the order of the information stored in the first half of , and storing it in the display memory area M, the stored information in the display memory area M is transferred at high speed to the display device to display the desired information on the display screen D. It is being displayed. The method shown in FIG. 3 is used to perform the above-mentioned conversion and transfer of the ordinal position of the stored contents. That is, the information stored in the buffer memory 1 is transferred to the display memory 2 through software processing, the storage position order is converted, and the information is stored in the order position to be displayed on the display screen. The information stored in the display memory 2 is sent out at high speed in the order in which it is stored under the control of a direct memory access (DMA) control circuit 3, and is converted into a drive signal for a cathode ray tube by a display control circuit 4. The display control circuit 4 also controls activation and termination of the DMA control circuit 3. However, as mentioned above, the information transfer from the buffer memory 1 to the display memory 2 is performed by software processing, so in order to transfer one screen's worth of information, the time Ta calculated by the following formula is required. .

Ta=Tcy×St×Ne×N _L However, Tey: Minimum operating cycle of the CPU St: Number of software execution steps (number of states) required to transfer one character Ne: Number of displayed characters per line M _L : One screen Number of display lines per display In addition, the above-mentioned information transfer needs to be performed every time the display contents change. Since changes in display contents occur frequently when inputting data or receiving data, the time required for such transfer is long. Furthermore, as the data communication speed increases, the processing time allocated to display control decreases, making it impossible to follow changes in input data. Information can be sent quickly from the display memory 2 to the display control circuit 4 according to instructions from the DMA control circuit 3. But something like this
Since DMA transfer simply repeatedly transfers information for one screen, the information array positions on the display screen and display memory must necessarily match. Further, the buffer memory 1 is composed of a memory that stores information for one screen or more, for example, over several pages, and the information in this memory is generally arranged in such a way that data can be easily transferred to the display memory. There is. However, since there is a case where the display is performed across the end part and the beginning part of the buffer memory, it is necessary to interpose the display memory 2.
information transfer is required, resulting in the drawbacks mentioned above.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display method that can solve the above-mentioned conventional drawbacks and shorten the processing time for screen control using software processing.

In order to achieve the above object, the display method of the present invention includes a buffer memory for storing information for one screen or more, a plurality of DMA control circuits, and the
A display control circuit is provided for instructing the DMA control circuit of a start address of transfer data, the number of data to be transferred, and an order of start of operation, and the plurality of DMA control circuits are each specified in the order specified by the display control circuit. The present invention is characterized in that address designation signals are sequentially sent out for a specified number of data from a starting address, so that stored data at a specified position is sent out from the buffer memory.

Next, the present invention will be explained in detail with reference to the drawings.
In this embodiment, the data in the buffer memory is transferred directly to the display control circuit without going through the display memory. FIG. 4 is a block diagram showing one embodiment of the present invention, which includes a buffer memory 1 in which information for one screen or more is stored, and DMA control circuits 31 and 3 that give address instructions to the buffer memory 1.
2, sets the start address, the number of data to be transferred, and the operation order in the DMA control circuits 31 and 32 to control their operations, and the buffer memory 1
The display control circuit 4 converts data sent from the display into a drive signal for a cathode ray tube (not shown). The display memory 2 used in the conventional example described above is not used. The buffer memory 1 has memory for several pages, and one page has a capacity to store data for one screen. Also,
Information to be displayed on the screen is sequentially input to the buffer memory 1. However, the starting positions are not the same. Each of the DMA control circuits 31 and 32 has a register (not shown), and stores therein a transfer start address, the number of data to be transferred, and a priority order instructed by the display control circuit 4, respectively. Then, in response to the DMA request signal from the display control circuit 4, the one with higher priority, e.g.
The DMA control circuit 31 starts the operation and sends out address designation signals that are sequentially incremented by 1 from the designated start address by the designated number of data.
When the specified number of data has been addressed, the priority is passed to the DMA control circuit 32, and the DMA control circuit 32
performs the same operation as described above. DMA control circuit 3
1 and 32 repeat the above operation alternately. The buffer memory 1 sequentially sends out data at storage locations designated by the above-mentioned DMA control circuit 31 or 32, and the sent data is sent to the display control circuit 4 where it is converted into a cathode ray tube drive signal and displayed on a cathode ray tube (not shown). be done.

Storage area B of buffer memory 1 according to this embodiment
An example of the relationship between the data storage position above and the display position on the display screen D is shown in FIG. In this example, the character information stored in the second half of the last page in the storage area B of buffer memory 1 is displayed in the upper half of the display screen D, and the character information stored in the first half of the first page in the storage area B is displayed in the upper half of the display screen D. Characters are displayed in the lower half of the display screen D. FIG. 6 shows a time chart of the state in which the DMA request signal from the display control circuit 4 and the addressing signal from the DMA control circuits 31 and 32 are sent in this case. In response to the DMA request signal, the designated address of the DMA control circuit 31 starts from the first address of the character information and advances to the last address of the character information, that is, the last address of the last page, and then the specified address of the DMA control circuit 31
The specified address starts from the first address of the character information, that is, the first address of the first page, and proceeds to the last address of the character information. If the DMA request signal is turned off here,
DMA transfer will stop. If the DMA request signal continues, the above-mentioned addressing signal will be sent repeatedly. In this way, the display screen D in FIG.
The characters shown in the figure below are displayed.

Next, another embodiment of the present invention will be described with reference to FIG. This embodiment includes n DMA control circuits 31 to 3n, and each
The DMA control circuit is the same as in the above case. In other words, the information to be displayed on the display screen 4 is
It is divided into sections or n sections, and the start address of the buffer memory 1 corresponding to each section, the number of data to be displayed, and the priority of DMA operation are stored in the respective DMA control circuits 31 to 3n. Each DMA control circuit receives data from the display control circuit 4.
In response to a DMA request signal, the DMA control circuit operates from the one with the highest priority, and when the operation of one DMA control circuit is completed, the operation shifts to the DMA control circuit with the next priority.
In this way, the screen can be divided into arbitrary display sections and characters can be displayed on the screen in an arbitrary order.
This is convenient when an indicator (status display) area or the like is provided within the display screen. It is also possible to configure so that the operation of the next DMA control circuit is started in response to a command from the display control circuit 4 each time, without setting the priority order of each of the above-mentioned DMA control circuits in advance. It is also possible to change the display of any section to another new character display during the display. In recent years, integrated circuits incorporating several channels of DMA control circuits are easily available, so the above implementation is easy and various modifications are also possible.

As described above, in the present invention, a plurality of
The configuration is such that the DMA control circuit is switched and operated to directly send out any number of data from any location in the buffer memory in any priority order, simplifying the software and making it easier to control the screen using software processing. Processing time can be significantly reduced. Furthermore, since the conventional display memory is not used, the memory capacity can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining scroll up; FIG. 2 is a diagram showing an example of a conventional information storage position;
Figure 3 is a block diagram showing the conventional display method, Figure 4
FIG. 5 is a block diagram showing an embodiment of the present invention. FIG. 5 is a diagram showing an example of information storage locations in the embodiment of FIG. 4. FIG. The chart and FIG. 7 are block diagrams showing other embodiments of the present invention. In the figure, 1... buffer memory, 2... display memory, 3... DMA control circuit, 4... display control circuit,
31, 32,..., 3n...DMA control circuit, B...buffer memory area, M...display memory area, D...display screen.

Claims (1)

[Claims] 1. A buffer memory for storing information for one screen or more, a plurality of direct memory access control circuits, a start address of data to be transferred to the direct memory access control circuit, the number of data to be transferred, and the order of start of operation. and a display control circuit for instructing the display control circuit, and each of the plurality of direct memory access control circuits sequentially specifies addresses for a specified number of data from each specified start address in accordance with the order specified by the display control circuit. A display method characterized in that a signal is sent out to cause the buffer memory to send out stored data at a designated position.