JPS6146860B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a diagnostic circuit in a data processing device.

In conventional data processing devices, circuit testing or diagnosis has been performed by cascading registers with a shift function to form a single shift path.However, in the case of a shift path in only one direction, even if there is a failure during the shift path, the failure will not occur. It is not possible to easily separate the parts, so even if one shift path is composed of circuits of a plurality of replacement units, it is necessary to replace all the circuit parts constituting the shift path in the event of a failure.
Furthermore, if a shift path is provided in both directions in order to easily isolate the failure location, the circuit becomes complicated and the amount of hardware increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device having a diagnostic circuit that can isolate a faulty part of a shift path by making it possible to test or diagnose a fixed shift path unit with a small amount of hardware.

In order to achieve the above object, the diagnostic circuit of a data processing device according to the present invention is formed by connecting a large number of shift registers, and includes a plurality of shift path units logically connected to each other, and a shift path unit output of the previous stage.
a shift path output signal switching circuit that outputs one of the shift path unit outputs of its own stage; a mode setting register in which the switching mode of the shift path output signal switching circuit is set by a predetermined value of a shift-in signal; The control circuit is separated from the unit and maintains the contents of the mode setting register during shift pass operation.

According to the above configuration, failure can be isolated for each circuit block including each shift path unit, and the object of the present invention is completely achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a data processing device according to the present invention, and is an example composed of a plurality of circuit blocks having shift paths formed by connecting a large number of shift registers and a control circuit thereof. In this embodiment, one shift path is formed by connecting two circuit blocks each including a fixed shift path unit.

In the figure, 3 indicates a terminal for connecting to the circuit block, and the circuit block is connected to the mode setting register 1 and the NAND circuits 31 to 34 and 36 to 3.
9 and controls the mode setting register 1 by separating it from the shift path, and shift registers 11 to 1n, and the circuit block is composed of a shift path output signal switching circuit 2 and shift registers 21 to 2m. The shift mode signal 101 is transmitted to the mode setting register 1, shift registers 11 to 1n, and shift registers 21 to 1n.
2m, and the clock signal 102 is the output 106 of an OR circuit composed of NAND circuits 32 to 34.
to mode setting register 1 through shift registers 11 to 1n, and shift registers 21 to 2m.
connected to. Mode switching signal 103 is NAND
The output 105 of the circuit 31 is connected to the NAND circuit 32, and the output 104 of the NAND circuit 31 is connected to the NAND circuit 33, the AND circuit 35, and
Connected to the NAND circuit 36.

Shift-in signal 201 is mode setting register 1
output 1 of this mode setting register 1.
07 goes to the NAND circuit 33, and the output 202 goes to the NAND circuit 33.
The output 203 of the OR circuit composed of NAND circuits 37 to 39 is connected to the shift register 11.
The shift-out signal 204 of the shift register 11 passes through n-2 shift registers, and the shift-out signal 205 of the shift register 1n is connected to one input of the shift path output signal switching circuit 2, and is also connected to the shift register 21. Ru. The shift out signal 206 of this shift register 21 is m-2
shift register 2 via shift registers
The shift out signal 207 of the shift register 2m is connected to the other input of the shift path output signal switching circuit 2, and the output 208 becomes the shift out signal. Further, the output 108 of the second bit of the mode setting register passes through the AND circuit 35 and becomes the output 109, which is supplied to the shift path output signal switching circuit 2 as a switching signal.

Next, the operation of shift path failure diagnosis will be explained.

In normal operation, the clock 102 is supplied with the mode switching signal 103 set to logic 0 and the shift mode signal 101 set to logic 1, so the shift-in signal passes through the paths 201-202-203-204-205-2.
Shifted out through 06-207-208. 201 to 208 first shift a mode value into the mode setting register 1 when a failure is detected and the failure location is divided into blocks, which are units of replacement. In this case, the a bit of the mode setting register 1 is set to logic 1, and the b bit is also set to logic 1. Next, mode switching signal 103
By setting this to logic 1, only the shift path on the circuit block side can be diagnosed. Mode switching signal 1
03, the output 105 of the NAND circuit 31 becomes a logic 0, and the value set in the a bit causes the output 107 to become a logic 0, and the NAND circuit 32
and 33, the supply of the clock signal 102 to the mode setting register 1 is stopped. Also,
The output 104 of the NAND 31 becomes logic 1, the output 109 of the AND circuit 35 becomes valid, and the b-bit value logic 1 is transmitted. As a result, the shift path output switching circuit 2 is switched and the output 205 of the shift path unit of the circuit block is changed. 208. Further, since the NAND circuit 38 is closed by the NAND circuit 36, the supply of the shift wait signal 202 to each shift path unit of the circuit block is cut off, and the mode setting register 1 is separated from the shift path. The shift path is formed as 201-203-204-205-208, and by supplying the clock in this state, the shift path of the block can be diagnosed regardless of the shift path of the block, so it is possible to isolate the failure location of both blocks. becomes possible.

As explained above, the present invention provides a shift path output switching circuit in a circuit block, and disconnects the mode setting register for setting the switching mode of the shift path output switching circuit from the shift path during operation to isolate the failure location, thereby diagnosing the shift path failure. It has an effect that can be easily achieved in block units.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. 1...Mode setting register, 2...Shift path output signal switching circuit, 3...Inter-block connection terminal,
11~1n・21~2m...Shift register, 3
1~34・36~39...NAND circuit, 35...
AND circuit.

Claims (1)

[Claims] 1. A plurality of shift path units that are formed by connecting a large number of shift registers and are logically connected to each other,
a shift pass output signal switching circuit that outputs either a shift pass unit output of the preceding stage or a shift pass unit output of the current stage; and a mode setting register in which a switching mode of the shift pass output signal switching circuit is set by a predetermined value of a shift-in signal. and a control circuit that separates the mode setting register from a shift pass unit and holds the contents of the mode setting register during a shift pass operation.