JPS6146979B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor memory device.
In particular, it is intended to realize electrically rewritable, high-density nonvolatile memory.

[Technical background of the invention]

Conventionally, the memory cell shown in Figure 1 has been known as a relatively high-density electrically rewritable non-volatile memory (EEPROM) memory cell, and its details can be found in, for example, the IEEE Journal of
Solid-State Circuits, Vol.SC-17, No.5,
PP821-827 (1982). The basic configuration of this memory cell is as follows. That is, in the figure, Q ₁ is a selection transistor, Q ₂ is a storage transistor with a floating gate (floating gate FG), and the drain of transistor Q ₂ is connected via the source and drain of transistor Q ₁ . Bit line BL
The source is connected to a source power line S. In addition, SG is Selection Gate,
CG is a control gate.

FIG. 2 shows a cross-sectional configuration of the circuit shown in FIG. 1 above. In the figure, the same components as in FIG. 1 are given the same reference numerals. On the P-type semiconductor substrate 11 are N ⁺ type impurity regions 12 ₁ , 12 ₂ , 1 that serve as source and drain regions of the transistors Q ₂ and Q ₁ .
2 ₃ is formed, and these impurity regions 12 ₁ , 12 ₂
Insulating layers 13 1 and 13 ₁ and 12 ₂ and 12 ₃ are provided between
₃₂ , a floating gate FG and a selection gate SG are formed. Further, a control gate CG is formed on the floating gate FG with an insulating layer 14 interposed therebetween. Now, the capacitance between the floating gate FG and the drain region ₁₂₂ of the transistor _Q2 is _C1 , and the capacitance between the control gate CG and the floating gate FG is C1.
C ₂ , floating gate FG and channel region 1
The capacitance between 5C ₃ and the floating gate
If the capacitance between FG and source region ₁₂₁ is _C4 ,
The relationship “C ₂ >C ₁ +C ₃ +C ₄ ” is established between each capacitance C ₁ to C ₄ .

The operation of the EEPROM described above is as described below. First, in the erase operation, a high voltage V _PP (usually 16 to 21 V) is applied to the selection gate SG and control gate CG, and the bit line BL and source power line S are set to OV. As a result, the transistor Q ₁ is turned on and the drain and source of the transistor Q ₂ are OV, and the control gate CG becomes V _PP , so C ₂ > C ₁ + C ₃
Since +C ₄ , floating gate FG is V _PP
The potential is closer to that of the floating gate FG and the source and drain regions 12.
₁ , 12 Add between ₂ . Insulating layer 13 ₁ is approximately 100 Å
Because it is extremely thin, a current called Fauler-Nordheim type flows between the source, drain, and floating gate FG, and electrons are stored in the floating gate FG.

Next, write V _PP to the selection gate
, OV to control gate CG, bit line
Apply V _PP to BL and 5V (or leave it open) to the source power supply line S. By doing this, since C ₂ > C ₁ + C ₃ + C ₄ , the electric field is mainly applied between the floating gate FG and the source and drain, and in turn electrons are applied to the floating gate.
Exit from FG to drain, floating gate
The negative charge accumulated in FG is reduced. Therefore, the threshold voltage of transistor _Q2 decreases and the threshold voltage becomes −
It becomes a depletion type of about 5V. Note that the reason why the source power supply line S is set at 5V or open is to cut off unnecessary current flowing from the drain to the source of the transistor _Q2 .

[Problems with background technology]

However, in the above configuration, when the source power line S is set to 5 V or left open when writing information, the source power line S becomes 5 V or higher even in unselected rows and columns. Therefore, an electric field is applied between the source power line S and the floating gate FG in the unselected cells, which has the disadvantage of deteriorating the charge retention characteristics. In other words, the voltage applied between the source and the floating gate causes electrons to flow out little by little, changing the stored information.

In addition, the insulating layer ₁₃₁ in FIG. is a polysilicon oxide film that is difficult to make thin, and has a film thickness of about 800 Å. Therefore, in order to satisfy the above-mentioned relationship of each capacitance "C ₂ > C ₁ + C ₃ + C ₄ ", it is necessary to overlap the control gate CG and floating gate FG as shown in the pattern plan view of Figure 3. Control gate with larger area
It was necessary to set a large capacitance C ₂ between the CG and the floating gate FG, making it difficult to achieve high integration.

[Purpose of the invention]

This invention was made in view of the above circumstances, and its purpose is to improve the selectivity and retention characteristics of memory cells, to achieve higher integration and reliability, and to improve write and An object of the present invention is to provide an excellent semiconductor memory device that can be easily erased.

[Summary of the invention]

That is, in the semiconductor memory device according to the present invention, a storage transistor that stores information by the charge of a floating gate, a selection transistor that selects this storage transistor, and an isolation transistor that separates the storage transistor from a common line. By providing a transistor as a unit storage cell and configuring the capacitance between the control gate and the floating gate of the storage transistor to be smaller than the sum of the capacitance between the floating gate, the drain region/channel region, and the source region, information can be stored. Erasing and writing are performed from the control gate side.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 shows an equivalent circuit of a unit memory cell. In the figure, _Q1 is a selection transistor, one end of the selection transistor _Q1 is connected to a bit line BL, and the other end is connected to one end of a storage transistor _Q2 . One end of the isolation transistor Q ₃ is connected to the other end of the storage transistor Q ₂ , and the source power line (common line) is connected to the other end of the isolation transistor Q ₃ .
S is connected to isolate the source region of the storage transistor Q ₂ from the source power supply line S. Note that the control gate CG of the storage transistor Q ₂ and the control gate CG of the isolation transistor Q ₃ are commonly connected.

FIGS. 5a and 5b show a pattern plan view of the circuit shown in FIG. 4 and a cross-sectional configuration diagram thereof taken along the line X-X'. In the figures, parts corresponding to those in FIG. Attach. selection gate
By SG and diffusion layers 16 ₁ and 16 ₂ , selection transistor Q ₁ is connected to control gate CG, floating gate FG and diffusion layers 16 ₂ and 16 ₃ .
The storage transistor Q ₂ is formed by the control gate CG and the isolation transistor Q ₃ is formed by the control gate CG and the diffusion layers 16 ₃ and 16 ₄ .

In the above configuration, the floating gate FG of the memory transistor Q ₂ and the diffusion layer 16
Capacitors C ₁ , C ₄ , and C ₃ formed between the control gate CG and the channel region ₁₆₀ are the same as those in FIG. ₁ , but are formed between the control gate CG and the floating gate FG _. The capacitance C ₂ is formed by laminated regions 17 ₁ and 17 ₂ in which the control gate CG and floating gate FG in FIG. Therefore, the capacitance C ₁ formed between the floating gate FG, the diffusion layers (source/drain regions) 16 ₂ , 16 ₃ and the channel region 16 ₀ of the substrate 11,
The capacitance C 2 formed between the control gate CG and the floating gate FG can be reduced from the sum of C ₄ and C ₃ ``C ₁ +C ₃ +C _{4 '} '.

According to such a configuration, the floating gate FG in the first layer and the control gate CG in the second layer, which are stacked via the insulating layer, are connected to the first floating gate FG and the control gate CG in the second layer, which are surrounded in parallel by the ends of the respective gates. , has second laminated regions 17 ₁ and 17 ₂ , and even if misalignment occurs between the first layer and the second layer during patterning, the sum of the areas of the laminated regions 17 ₁ and 17 ₂ is Always constant. That is, since the capacitance between the control gate CG and the floating gate FG is always constant, the ratio between the capacitance C ₂ and C ₁ +C ₃ +C ₄ can be set accurately.

The operation in the above configuration will be explained.
First, in the erase operation, a voltage exceeding the threshold voltage of the selection transistor _Q1 is applied to the selection gate SG.
For example, _a high voltage _VPP of 5V to VPP is applied to the control gate CG, and the bit line BL and source power line S are set to OV. Since the sum of C ₁ , C ₃ and C ₄ is larger than the capacitance C ₂ , the electric field generated by the potential difference between the control gate CG and the source, drain, and channel mainly affects the floating gate FG and the control gate CG. join in between. This applies a large electric field between the floating gate FG and the control gate CG of the storage transistor Q ₂ , and the Feurer-Nordheim current flows between the floating gate FG and the control gate CG, causing electrons to be controlled from the floating gate FG. It escapes to the gate CG, and the threshold voltage of the memory transistor _Q2 becomes negative, becoming a depletion type. At this time, the drain and source of transistor _Q2 are both OV and at the same potential, so no unnecessary channel current flows.

On the other hand, when writing, selection gate SG is set to V _PP and control gate CG is set to OV.
Set to . Then, when a high voltage V _PP is applied to the bit line BL of the memory cell to be programmed, the drain of the storage transistor Q ₂ receives a voltage "V _PP -V" which is lowered by the threshold voltage V _TH1 of the selection transistor Q ₁ .
A potential _TH1 is applied. Since erasing has been performed before writing, the threshold voltage V _TH2 of the storage transistor Q ₂ is negative, and an inversion layer is formed in the channel region of this transistor Q ₂ . Therefore floating gate FG
Since the value of the capacitance C ₃ between the channel region 160 and the channel region ₁₆₀ is large, and the transistor Q ₂ is in a conductive state, the source side node B and the drain side node A are at the same potential. Therefore, floating gate
FG is pulled up to a high potential by the sum of each capacitance "C ₁ + C ₃ + C ₄ ", and a strong electric field is applied between the control gate CG and the floating gate FG, causing the electric field to flow from the control gate CG to the floating gate FG. Electrons flow in and the floating gate FG becomes negatively charged. Due to this negative charging of the floating gate FG, the threshold voltage V _TH2 of the storage transistor Q ₂ is shifted in the positive direction, making it an enhancement type transistor. At this time, if the isolation transistor _Q3 is a normal enhancement type, it is in a non-conductive state because the control gate CG is at OV and the source power supply line S is at OV.
In this case, as will be described later, during reading, it is necessary to raise the potential of the control gate CG to about 1 to 3 V so that the isolation transistor _Q3 becomes conductive. In order to be able to read data when the potential of the control gate CG is OV, the isolation transistor _Q3 may be made of a depletion type. In this case, the potential of the source power line S may be set to be equal to or higher than the absolute value |V _TH3 | of the threshold voltage V _TH3 of the isolation transistor Q ₃ during writing.

According to such a configuration, the control gate
Since the CG and the floating gate FG overlap each other at their gate ends, the electric field concentration effect generated at these ends facilitates erasing/writing operations. In addition, since the isolation transistor Q ₃ is provided, even if the channel length of the storage transistor Q ₂ is set short, this transistor is not used during writing.
Punch-through phenomenon between the source and drain of Q ₂ can be prevented, improving reliability.

FIG. 6 is a pattern plan view showing another embodiment of the invention. In the figure, the same components as those in FIG. In other words, when using three gate wiring layers, the floating gate FG is placed in the first wiring layer, and the control gate is placed in the second wiring layer.
A select gate SG is formed in the third wiring layer of the CG, and the select gate SG is configured to cover the floating gate FG. Therefore, the selection transistor _Q1 and the storage transistor _Q2 are formed in succession, and the diffusion layer ₁₆₂ in FIG. 5b can be made unnecessary.
Even higher integration can be achieved.

〔Effect of the invention〕

As explained above, according to the present invention, an excellent semiconductor memory device can be obtained which can improve the selectivity and retention characteristics of memory cells, achieve higher integration, improve reliability, and facilitate writing and erasing. It will be done.

[Brief explanation of the drawing]

1 to 3 are a circuit diagram, a cross-sectional configuration diagram thereof, and a pattern plan view of a conventional semiconductor memory device (EEPROM), and FIG. 4 is an equivalent circuit diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 5 is a diagram showing an example of the pattern configuration of the circuit shown in FIG. 4,
FIG. 6 is a pattern plan view showing another embodiment of the present invention. Q ₁ ...selection transistor, Q ₂ ...memory transistor, Q ₃ ...isolation transistor, CG...
...Control gate (control gate), FG...Floating gate (floating gate), S...Source power line (common line), BL...Bit line, 17
₁ , 17 ₂ ...Lamination area.

Claims (1)

[Claims] 1. A storage transistor that stores information using the charge of a floating gate, a selection transistor that selects this storage transistor, and an isolation transistor that separates the storage transistor from a common line. The memory transistor is provided as a unit memory cell, and the memory transistor is configured such that the capacitance between the control gate and the floating gate is smaller than the sum of the capacitances between the floating gate, the drain region, the channel region, and the source region. semiconductor storage device. 2 The memory transistor has a control gate and a floating gate stacked on each other with an insulating layer interposed therebetween and surrounded in parallel by respective gate ends.
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is patterned to have a laminated region.