JPS6147630A - Adjustment of n type carrier concentration distribution in gallium arsenic semiconductor - Google Patents

Adjustment of n type carrier concentration distribution in gallium arsenic semiconductor

Info

Publication number
JPS6147630A
JPS6147630A JP59168844A JP16884484A JPS6147630A JP S6147630 A JPS6147630 A JP S6147630A JP 59168844 A JP59168844 A JP 59168844A JP 16884484 A JP16884484 A JP 16884484A JP S6147630 A JPS6147630 A JP S6147630A
Authority
JP
Japan
Prior art keywords
concentration distribution
substrate
composition ratio
carrier concentration
arsenic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59168844A
Other languages
Japanese (ja)
Inventor
Takashi Sato
孝 佐藤
Koichi Ishida
石田 宏一
Kazutaka Terajima
一高 寺嶋
Tsuguo Fukuda
承生 福田
Masato Nakajima
真人 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP59168844A priority Critical patent/JPS6147630A/en
Publication of JPS6147630A publication Critical patent/JPS6147630A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00Ion implantation into wafers, substrates or parts of devices
    • H10P30/20Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PURPOSE:To adjust carrier concentration distribution of N type layer after ion implantation by selecting a fused composition ratio of gallium and arsenic on the occasion of manufacturing a semi-insulating gallium arsenic substrate. CONSTITUTION:A semi-insulating gallium arsenic single crystal substrate is manufactured with the liquid sealing lifting method by selecting a fused composition rate of gallium and arsenic in the range of 0.500-0.505 and it is then subjected to the heat processing by ion implantation to such substrate. For example, a substrate is cut away from an ingot by lifting a crystal using fused solution having the fused composition ratio in said range and the Si ion is implanted to such crystal substrate under the condition of 150keV and 3X10<12>cm<-2>. Thereafter, the heat processing is carried out under the ambient of 850 deg.C, 30min, As pressure (PA84-100Torr). Thereby, the N type carrier concentration distribution depends on the fused composition ratio, and moreover an electrical conductive layer having less fluctuation, excellent uniformity and controlability can be obtained.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 この発明は、ガリウム砒素半導体におけるn形キアリア
ー濃度分布の調整法に関する。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for adjusting n-type chiaria concentration distribution in a gallium arsenide semiconductor.

〈従来の技術〉 ■−■族化合物半導体のうち、ガリウム砒素(Ga、A
s)は電子移動度が太きく、シかも高品質のGaA、の
比抵抗が10″Q−α以上と高絶縁性であること、結晶
内の欠陥が少く、分布が絢−であるものが得られること
、大型ウェハーの製造が容易であること等の理由によシ
超高速集積回路、光−電子集積回路の素子用結晶基板と
して広く用いられつつある。
<Conventional technology> Among the ■-■ group compound semiconductors, gallium arsenide (Ga, A
s) is high-quality GaA with high electron mobility, high insulating properties with a resistivity of 10"Q-α or more, few defects in the crystal, and a fine distribution. Because of its high availability and ease of manufacturing large wafers, it is becoming widely used as a crystal substrate for elements of ultrahigh-speed integrated circuits and opto-electronic integrated circuits.

このような要求を満すGcLAs単結晶の製造方法とし
ては、原料を直接合成する高圧液体封止引き上げ法が知
られており、高品質な単結晶が製造されている。
As a method for producing a GcLAs single crystal that satisfies such requirements, a high-pressure liquid seal pulling method in which raw materials are directly synthesized is known, and high-quality single crystals are produced.

一方、この単結晶を集積回路の結晶基板として用いると
きはウェーハ状に切断し、通’/;” Siイオン等の
不純物をイオン注入法などにより添加し、更にSi原子
を電気的に活性化するため800〜900℃の熱処理を
施し、n形の電気伝導層を形成する。
On the other hand, when this single crystal is used as a crystal substrate for an integrated circuit, it is cut into wafers, impurities such as Si ions are added by ion implantation, and the Si atoms are electrically activated. Therefore, heat treatment is performed at 800 to 900°C to form an n-type electrically conductive layer.

〈発明が解決しようとする問題点〉 以上の製造法において熱変成を押え、電気特性の一様な
電気伝導層を形成することは高性能の各種素子を分留シ
、及び再現性良く製造する上では不可欠な要件であるが
、従来上述のように液体封止法によシ成長させた結晶基
板を使用してイオン注入法によpn形層を形成する場合
、制御性良く、一様な電気伝導層を形成することが極め
て困難であった。
<Problems to be solved by the invention> By suppressing thermal transformation and forming an electrically conductive layer with uniform electrical properties in the above manufacturing method, it is possible to produce various high-performance devices by fractionation and with good reproducibility. This is an essential requirement, but when forming a pn-type layer by ion implantation using a crystal substrate grown by liquid sealing as described above, it is necessary to form a pn-type layer with good controllability and uniformity. It was extremely difficult to form an electrically conductive layer.

そこで、この発明はガリウム砒素半導体において熱変性
が少々<、且つ電気特性の一様な電気伝導度を形成する
n形キアリアー濃度分布の調整法を提供することを目的
とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for adjusting the n-type carrier concentration distribution in a gallium arsenide semiconductor, which causes little thermal denaturation and forms electrical conductivity with uniform electrical characteristics.

〈問題点を解決するだめの手段〉 本願発明者等の実験によれば、イオン注入法によって形
成されたn形層のキアリアー濃度分布は注入イオン原子
の作るキアリアーのみならずイオン注入前の半絶縁性ガ
リウム砒素基板の製造工程に依存している、即ちs5原
子等の注入原子はGαα空孔−はM空孔を占有する必要
があるが、この場合のキアリアー濃度分布は電気的に活
性化された結晶基板の欠陥によっても影響を受けること
が判明した。
<Means to Solve the Problem> According to experiments conducted by the inventors of the present application, the carrier concentration distribution in the n-type layer formed by the ion implantation method is not limited to carriers formed by implanted ion atoms, but also to the semi-insulating layer before ion implantation. In other words, implanted atoms such as s5 atoms need to occupy Gαα vacancies and M vacancies, but the chiaria concentration distribution in this case depends on the manufacturing process of the gallium arsenide substrate. It was found that defects in the crystal substrate also affected the effect.

具体的には、半絶縁性ガリウム砒素基板を製造する際の
ガリウムと砒素の融液組成比を選択することによってイ
オン注入後のn形層のキアリアー濃度分布を調整できる
ことが判明j〜だ7、そこで、この発明ではガリウムと
砒素の融液組成比(占)を0−500〜0.505 の
範囲内で選択して液体封止引き上は法によυ半絶縁性カ
リウム砒素単結晶基板を製造し、更に詐基板のウェーハ
を常法に従いイオン注入して熱処J】1!するものであ
る。
Specifically, it has been found that by selecting the composition ratio of gallium and arsenic melt when manufacturing a semi-insulating gallium arsenide substrate, the chiaria concentration distribution in the n-type layer after ion implantation can be adjusted. Therefore, in this invention, the melt composition ratio of gallium and arsenic is selected within the range of 0-500 to 0.505, and the semi-insulating potassium arsenide single crystal substrate is fabricated by the liquid sealing method. After manufacturing, the wafer of the false substrate is ion-implanted and heat treated according to the conventional method J】1! It is something to do.

〈発明の効果〉 以上の範囲内でガリウムと砒素の融液組成比を選択して
ガリウム砒素のn形半導体を形成すると、そのn形キア
リアー濃度分布は融液組成比に依存し、しかもバラツキ
も少なく均一で制御性良好なMl電気伝導層得られる。
<Effects of the Invention> When a gallium arsenide n-type semiconductor is formed by selecting the melt composition ratio of gallium and arsenic within the above range, the n-type carrier concentration distribution depends on the melt composition ratio, and there is also no variation. A uniform Ml electrically conductive layer with a small amount and good controllability can be obtained.

〈実施例〉 実施例1 GaAs単結晶を液体封止引き上げ法によって製造する
際の融液組成比とイオン注入によって形成されたn形層
のキアリアー濃度分布の依存性を調べるために、五種類
の結晶インゴットを用意した。
<Example> Example 1 In order to investigate the dependence of the melt composition ratio when manufacturing a GaAs single crystal by the liquid-sealed pulling method and the chiaria concentration distribution of the n-type layer formed by ion implantation, five types of A crystal ingot was prepared.

ここで、各結晶インゴットは0.488〜0.509の
範囲の融液組成比を有する融液を用いて同一の条件で結
晶を引き上げて行うことにより製造した。以後各インゴ
ットから基板を切シ出し、それぞれの結晶基板にsiイ
オンを150 KeV 5 X 1012(m−”の条
件下で注入し、850℃30 min 、 A8圧力(
PA!14〜1’00TOrγ)の雰囲気下で熱処理を
行なった。
Here, each crystal ingot was manufactured by pulling crystals under the same conditions using a melt having a melt composition ratio in the range of 0.488 to 0.509. Thereafter, a substrate was cut out from each ingot, and Si ions were implanted into each crystal substrate under the conditions of 150 KeV 5 × 1012 (m-'') at 850° C. for 30 min and A8 pressure (
PA! The heat treatment was performed in an atmosphere of 14 to 1'00 TOrγ).

その後、直径500μ情のAtをショットキー電極とし
て21間隔で基板面上に形成し、C−V法によるキアリ
アー濃度分布を測定した。
Thereafter, Schottky electrodes having a diameter of 500 μm were formed on the substrate surface at 21 intervals, and the Schottky electrode concentration distribution was measured by the CV method.

得られたキアリアー濃度分布は基板面上の各位置で異な
っているため、最上方と最下方に偏位した分布の、それ
ぞれの各位置における平均キアリアー濃度を算出し、新
たに平均キアリアー濃度分布を求めた。第1図に融液組
成比が0.48B、0.502.0゜509の場合の結
晶インゴット中心部から切シ出された基板のキアリアー
濃度分布を示す。同図には0.500.0.505の結
果は示されていないが0.502と同じような分布であ
る。
Since the obtained Chiaria concentration distribution differs at each position on the substrate surface, the average Chiaria concentration at each position of the distribution shifted to the top and bottom was calculated, and a new average Chiaria concentration distribution was calculated. I asked for it. FIG. 1 shows the chiaria concentration distribution of the substrate cut out from the center of the crystal ingot when the melt composition ratio is 0.48B, 0.502.0°509. Although the results of 0.500 and 0.505 are not shown in the figure, the distribution is similar to that of 0.502.

第1図から明らか々ように、上記融液組成比の違いによ
りキアリアー濃度分布が異なり、融液組成比による依存
性がある。
As is clear from FIG. 1, the Chiaria concentration distribution differs depending on the above-mentioned melt composition ratio, and there is a dependence on the melt composition ratio.

実施例2 更に、詳細な融液組成比依存性をi’j11t1べるた
めに、基板面内で測定されたキアリアー濃度分布のバラ
ツキの程度をキアリアー濃度分布のピーク値(Np )
とL8B理論分布からのずれ(Δ×)で評価を行なった
、Np及びΔ×の定義は第2図に示す。第3図に融液組
成比に対するNPとΔ×の平均値とその標準偏差を誤差
棒の長さとして表わす、−1この図から明らかなように
、組成比。、500〜0.505のわずかにAs過剰で
結晶成長された基板を使用した場合の方がバラツキも少
なく急峻な分布が得られた。
Example 2 Furthermore, in order to understand the detailed dependence on the melt composition ratio, the degree of variation in the carrier concentration distribution measured within the substrate plane was expressed as the peak value of the carrier concentration distribution (Np).
The definitions of Np and Δx are shown in FIG. 2, where the evaluation was performed based on the deviation (Δx) from the L8B theoretical distribution. FIG. 3 shows the average value of NP and Δ× and its standard deviation with respect to the melt composition ratio as the length of the error bar. -1 As is clear from this figure, the composition ratio. , 500 to 0.505, where the crystals were grown with a slight excess of As, a steeper distribution with less variation was obtained.

これ等の結果からキアリアー濃度分布はSi原子の作る
キアリアーのみならず融液組成に関係する他のを因によ
り影響を受けるととが明らかになシ、そして0,500
〜0.505の組成比で作られた基板のn形キアリアー
の急峻な濃度分布はイオン注入法によるSi原子濃度分
布に近く、均一で制御性の良い電気伝導層が形成された
From these results, it is clear that the chiaria concentration distribution is influenced not only by chiaria produced by Si atoms but also by other factors related to the melt composition.
The steep concentration distribution of n-type carriers in the substrate made with a composition ratio of ~0.505 was close to the Si atom concentration distribution obtained by ion implantation, and a uniform electrically conductive layer with good controllability was formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、GaとAsの融液組成比とギアリアー濃度分
布の関係を示す図、第2図はギアリアー濃度分布とL8
B理論分布との関係を示す図、第6図はGaとAsの融
液組成比に対するギアリアー濃度分布のピーク値(Np
)とLs8理論分布からのずれ(Δ×)の平均値とその
標準偏差の関係を示す図である。 特許出願人  工業技術院長 川[] 第1間 00.5 表向IXらΦユ粱交(μm) 第2YM 表面力1夕の塚2 第31!! As/(Go+As)
Figure 1 shows the relationship between the Ga and As melt composition ratio and Gearia concentration distribution, and Figure 2 shows the relationship between Gearia concentration distribution and L8
Figure 6 shows the relationship between the B theoretical distribution and the peak value of the Gearia concentration distribution (Np
) is a diagram showing the relationship between the average value of the deviation (Δ×) from the Ls8 theoretical distribution and its standard deviation. Patent Applicant Director of the Agency of Industrial Science and Technology Kawa [] 1st interval 00.5 Omuka IX et Φ Yu Riko (μm) 2nd YM Surface force 1 Yunotsuka 2 31st! ! As/(Go+As)

Claims (1)

【特許請求の範囲】[Claims] ガリウムと砒素の融液組成比を0.500〜0.505
の範囲内で選択して液体封止引き上げ法により半絶縁性
ガリウム砒素単結晶基板を製造し、更に該基板上にイオ
ン注入して熱処理することを特徴とするガリウム砒素半
導体におけるn形キアリアー濃度分布の調整法。
The melt composition ratio of gallium and arsenic is 0.500 to 0.505.
n-type carrier concentration distribution in a gallium arsenide semiconductor, which is characterized by manufacturing a semi-insulating gallium arsenide single crystal substrate by a liquid seal pulling method by selecting within the range of adjustment method.
JP59168844A 1984-08-14 1984-08-14 Adjustment of n type carrier concentration distribution in gallium arsenic semiconductor Pending JPS6147630A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59168844A JPS6147630A (en) 1984-08-14 1984-08-14 Adjustment of n type carrier concentration distribution in gallium arsenic semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59168844A JPS6147630A (en) 1984-08-14 1984-08-14 Adjustment of n type carrier concentration distribution in gallium arsenic semiconductor

Publications (1)

Publication Number Publication Date
JPS6147630A true JPS6147630A (en) 1986-03-08

Family

ID=15875578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59168844A Pending JPS6147630A (en) 1984-08-14 1984-08-14 Adjustment of n type carrier concentration distribution in gallium arsenic semiconductor

Country Status (1)

Country Link
JP (1) JPS6147630A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5988394A (en) * 1982-11-12 1984-05-22 Agency Of Ind Science & Technol Manufacturing device for gallium arsenide single crystal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5988394A (en) * 1982-11-12 1984-05-22 Agency Of Ind Science & Technol Manufacturing device for gallium arsenide single crystal

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