JPS6148708B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a photomask for integrated circuits.

Conventionally, when a photoetch pattern for forming an integrated circuit on a semiconductor substrate is transferred to photoresist and etched, the pattern is etched on the backside of the wafer or on the scribe line used to separate the integrated circuit pattern chips, or on the same substrate. A completely white or black blank die, which is prepared as a die and has a size equal to or larger than the integrated circuit pattern chip, is used as an etching monitor to ensure that the integrated circuit pattern is etched accurately. However, in recent years, as the chip area of integrated circuits has become larger and it has become necessary to perform complex etching in which the thickness of the etched portion is not just one, but many different types, the above-mentioned It has become impossible to perform accurate etching by using such scribe lines or blank dies as etching monitors. The reason for this is that even if, for example, a thin film of the same thickness is to be etched twice, the above-mentioned scribe line or blank die can only be used as a one-time etching monitor.

One way to solve this problem is to separately prepare a monitor wafer with conditions suitable for etching and then perform the etching. However, this method is not suitable for etching under strict conditions where wafer-to-wafer variations are a problem, and furthermore, if the production wafers have a wide variety of manufacturing conditions, it is necessary to prepare monitor wafers for all types. This has the disadvantage that the etching process becomes very complicated.

Therefore, it is an object of the present invention to solve the above-mentioned disadvantages of the conventional method, and to be able to perform etching even when performing complex etching where the film thickness of the etched portion varies widely, and even when etching is performed on a large scale integrated circuit. Even if it is a chip, it is possible to perform the same etching as in the normal integrated circuit manufacturing process.
The goal is to provide masks.

An embodiment of the invention is shown in FIGS. 1 and 2. In other words, this photomask for integrated circuits is
As shown in FIG. 1, a plurality of mask patterns 2 for integrated circuits that are actually required as a product are arranged vertically and horizontally on a glass surface 1, and one corner of the array position is used as a mask pattern for forming an etching monitor chip. This is used as pattern 3.

A mask for forming the etching monitor chip.
Pattern 3, as shown enlarged in Figure 2A,
A rectangular white pattern 4 and a rectangular black pattern 5 whose longitudinal dimension is the length of one side are combined in a grid in a rectangular area given by the area of one chip of an integrated circuit.

In photoetching for forming integrated circuits, multiple photomasks are used as a set.
For example, when etching two types of film thickness, in order to monitor the etching of the two types of film thickness, the etching monitor chips of other photomasks in the same group are used as shown in FIG. 2B. The forming mask pattern 3' is a lattice-like black and white pattern such that the white pattern 4 formed on the photomask overlaps, at least in part, the formation position of the black pattern 5' of another photomask. The division positions of 4' and 5' are made different from those of the previous photo mask.

An example in which the above-mentioned embodiment in which the mask pattern for forming an etching monitor chip is formed by dividing it into two photomasks will be used in an actual photoetch process will be described below. Note that for the sake of simplicity, the resist used will be described as a positive type.

In the first step of this photo-etching process, as shown in FIG. 3A, the surface of the semiconductor substrate 6 is etched.
After forming the SiO ₂ film 7, in the subsequent photo-etching step, a desired photo-etch pattern is formed on the SiO ₂ film 7 using photoresist 8, as shown in FIG. 3B.

After removing the photoresist 8, a diffusion layer 9 having a conductivity type opposite to that of the semiconductor substrate 6 is formed by a method such as gas diffusion or ion implantation, as shown in FIG. 3C.

Thereafter, when a new SiO ₂ film 10 is formed by an oxidation method as shown in FIG. 3D, two types of film thickness layers a and b are generated.

This photo-etching process then removes the SiO ₂ film having the two types of film thickness layers a and b as shown in FIG. 3E.
Proceeding to the etching step of the film 10, when etching is performed with the removal of the thick film layer a as the reference, the photoetch pattern is completely transferred onto the semiconductor substrate 6, and the etching is performed with the removal of the thin film layer b as the reference. By doing this, it _is possible to leave a thin oxide film layer in the thick layer a portion and use the remaining part as an insulating film in the subsequent steps. The subsequent steps will differ depending on whether the material is etched or not.

In such a case, the photo-etching process (third
By forming black and white patterns 4 and 5 as shown in FIG. 2A as a photomask etching monitor chip forming mask pattern used in FIG. The cross-sectional structure of the etching monitor chip portion formed on 6 is indicated by reference numeral 1 in FIG. 4A.
1, and after subsequent gas diffusion, ion implantation, oxide film formation, etc., the SiO ₂ film shown in FIG. 3D is formed for an integrated circuit as shown in FIG. 4B. Two types of film thickness layers a' and b' similar to 10 are formed. Therefore, when etching the two types of film thickness layers a and b formed for integrated circuits, this etching monitor chip (fourth
Etching can be performed by selecting one of the two types of thick film layers a' and b' shown in Figure B) as a reference. That is, when etching monitoring is performed using the thick film layer a' as a reference, the thickness of the etching monitor chip (FIG. 4B) corresponding to the white pattern 4' of the mask pattern 3' shown in FIG. 2B is When the film layer a' is etched as shown in FIG. 4C and the etching is monitored using the thin film layer b' as a reference, the white pattern 4 of the mask pattern 3' shown in FIG. The thin film layer b' of the etching monitor chip (FIG. 4B) corresponding to ' is etched as shown in FIG. 4D, leaving a part of the thick film layer a'.

In the above embodiment, the etching monitor chip was shown for a very simple example, so the mask pattern was represented by a black and white quadrant grid pattern. However, the etching monitor chip corresponding to the actual process is more complex. Needless to say, it will become something. Further, the mask pattern does not need to be an equally divided black and white checkered pattern, and it is better if it can faithfully represent each process of an actual integrated circuit. In practice, a black and white checkered pattern with 8 divisions is preferable, and this monitor pattern for forming an etching monitor chip is suitable for forming an etching monitor chip so that, for example, when etching a SiO ₂ film, water repellency can also be monitored. It is preferable that the edge of the mask pattern protrudes beyond the edge of the semiconductor substrate. In addition, in both the case of a water-repellent monitor and the case of a color monitor, the width of the black and white pattern of the mask pattern needs to be 10 μm or more.

With this configuration, the etching monitor chip 11 corresponding to the SiO ₂ film 10 having two types of film thickness layers a and b, which is produced for the actual formation of an integrated circuit, can be formed on the same substrate during the same process. The etching can be selectively monitored depending on which of the two thickness layers a and b for actual integrated circuit formation is to be etched. The etching process for forming the actual integrated circuit can be performed with great precision.

In addition, in the etching step shown in FIG. 3E, when etching is performed using thin film layer b as a reference and the difference between thick film layer a and thin film layer b is used as an insulating film or a diffusion stopper in subsequent steps,
By using the photomask, it is possible to perform over-etching and make the difference between the thick film layer a and the thin film layer b extremely thin, which is suitable for just etching.

Furthermore, by using this photo mask, it is possible to form an etching monitor chip for each wafer, so the etching monitor chip can be used for each wafer to determine the actual diffusion sheet resistance and diffusion depth. can be measured without using a separate monitor wafer.

In addition, since an etching monitor chip can be formed for each wafer, even when etching several wafers with slightly different film thicknesses in the same batch, unlike monitoring only one monitor wafer, all wafers can be etched. It is possible to monitor water repellency, etc., and to perform accurate etching.

As described above, in the integrated circuit photomask of the present invention, at least one of the plurality of mask patterns arranged is a mask pattern for forming an etching monitor chip, and this mask pattern is divided into a white pattern and a black pattern. Because it is configured with a combination of etching techniques, it is easy to use the etching monitor for chip formation when designing a mask, even when performing complex etching where the etched portion has a wide variety of film thicknesses, or even when processing a large-scale integrated circuit chip. - By designing the pattern correctly, one wafer can be used as a monitor wafer, making it possible to perform accurate etching in the normal etching process, and manufacturing integrated circuits accurately and efficiently. It has the effect of being able to.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an embodiment of the present invention, FIGS. 2A and B are enlarged plan views of a mask pattern for forming an etching monitor chip, and FIG. 3 is a plan view showing the formation of an integrated circuit applied to the embodiment. FIG. 4 is an explanatory diagram of the process of forming an etching monitor chip according to the embodiment. DESCRIPTION OF SYMBOLS 1... Glass surface, 2... Mask pattern for integrated circuit, 3, 3'... Mask pattern for forming monitor chip, 4, 4'... White pattern, 5, 5'... Black pattern, 6... Substrate, 7, 10... SiO ₂ film, 8... Photoresist, 9... Diffusion layer, 11... Etching monitor chip.

Claims (1)

[Scope of Claims] 1. At least one of the plurality of mask patterns arranged is a mask pattern for forming an etching monitor chip, and this mask pattern is composed of a combination of a white pattern and a black pattern. Photomask for integrated circuits. 2. The white pattern is formed so as to overlap at least in part with the formation position of the black pattern of the etching monitor chip forming pattern of another integrated circuit photomask of the same group. photomask for integrated circuits.