JPS6148720B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a speech recognition device, and more particularly to a speech recognition device characterized by its data compression method.
Conventionally, speech recognition devices have been large-scale devices using large computers or minicomputers, and have only been partially put into practical use in industry as recognition devices limited to speakers. When applying a speech recognition device to consumer equipment, it is necessary to have a compact and low-cost configuration, and therefore, it is necessary to use a configuration that uses less memory and has a high recognition calculation processing speed. In this case, the fact that less memory is used means that the recognition performance is high relative to the capacity of the memory used. The present invention provides a speech recognition device that has high recognition performance considering the memory capacity used, and particularly provides a speech recognition device that is characterized by its data compression method. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the general structure of the speech recognition apparatus of the present invention. In the figure, 1 is a microphone, 2 is an amplification circuit for amplifying the microphone output, 3 is a filter consisting of bandpass filters 4, 4, etc. each having a different overband, and 5 is an analog-to-digital conversion circuit (hereinafter referred to as A). /D), 6
is an arithmetic circuit, 7 is an audio storage circuit included in the arithmetic circuit 6, and 8 to 9 are control signal output terminals of the arithmetic circuit 6. Arithmetic circuit 6 includes CPU, POM, RAM,
The main component is a microcomputer made up of I/O ports, etc. The operation of the voice recognition device of the present invention is to utter a voice corresponding to the control contents into a microphone in advance, and to store a characteristic pattern corresponding to the uttered voice in a memory location corresponding to the control contents. The registered state of the voice stored in the circuit 7 and the characteristic pattern corresponding to the uttered voice are calculated and compared to which of the registered voice characteristic patterns the characteristic pattern corresponding to the uttered voice is generally similar, and the uttered voice is The state is divided into two: a recognition state in which a control signal corresponding to the state is output; Even in the registered state, the voice characteristic pattern is
They are also common in cognitive states. The method for creating this voice feature pattern will be described below. For example, when a person utters [1] into the microphone 1, the output of the microphone 1 is amplified by the amplification circuit 2 and input to the filter 3. The filter 3 passes each predetermined overfrequency band component of the audio signal provided by the amplification circuit 2, converts it into its envelope voltage using an appropriate LPF, and outputs the converted signal. FIG. 2 is a diagram showing the output of the filter 3 in this case. In this Figure 2, FLT
1, FLT2, ...FLT8 is the frequency band of the audio signal
This is the envelope voltage output value of the filter that divides 100Hz to 5KHz into every 0.7 octave.
FLT1, FLT2... The output of the filter 3 is input to the A/D 5, sampled at fixed time intervals (approximately 10 milliseconds), and input to the arithmetic circuit 6 as an 8-bit digital value. Therefore,
8-bit information corresponding to FLT1 to FLT8 is 1
At the time of sampling, the signals are input to the arithmetic circuit 6 at the same time, and the arithmetic circuit 6 converts this into eight pieces of 2-bit information. The conversion means converts 8-bit data into 2-bit data by calculating the average value of each filter output value and comparing it with a value obtained by multiplying this value by a predetermined constant. Next, FIG. 3 shows a specific configuration of the arithmetic circuit 6 that converts 8-bit information into 2-bit information. In the figure, 10 is a clock pulse generation circuit,
A/D 5, addition circuit 11, delay circuit 12, multiplication circuits 13, 14, 15, and address control circuit 16
Supplies clock pulses to This addition circuit 11
is an addition circuit that adds the output of A/D6,
The output values of FLT ₁ to FLT ₈ at one sampling point are added in synchronization with the sampling clock T ₁ of A/D 6, and the output is

[Formula] is output to the multiplication circuits 13, 14, and 15. This multiplication circuit 13,1
4 and 15 are 1.2 times and 1.0 times the addition output ΣFi, respectively.
The signal is multiplied by 0.8 and output to comparison circuits 17, 18, and 19. Further, the delay circuit 12 delays the output of the A/D 6 at one sampling time by the time during which the output of the A/D 6 is calculated by the addition circuit 11 and the multiplication circuits 13, 14, and 15. 2
Reference numeral 0 designates a start-end detection circuit which receives the output of the amplifying circuit 2 and detects the start and end of the voice, and 21 a selection switch which selects the voice registration state and recognition state. Further, the address control circuit 16
inputs the outputs of the clock pulse generation circuit 10, the start end-end detection circuit 20, and the selection switch 21, and inputs the characteristic pattern of the sound into the sound storage circuit 7 and stores it, or compares the input sound with the registered sound. The degree of coincidence is calculated and an address for each storage circuit is created each time a control signal is output. Comparison circuits 17, 18, 19 are multiplication circuits 13, 14,
15 outputs (1.2×ΣFi), (1.0×ΣFi), (0.8×
ΣFi) and the output value Fi of the filter 3 delayed by the delay circuit 12.
Note that the output of the delay circuit 12 is transmitted to the multiplier circuits 13, 14,
The signal is input to comparison circuits 17, 18, and 19 so that the scale is eight times that of the output of signal 15. 22 is a code conversion circuit, and 23 is an initial storage circuit for temporarily storing voice characteristic patterns. Reference numeral 24 denotes a pattern storage circuit for storing voice registration patterns, and both storage circuits 23 and 24 constitute the voice storage circuit 7. Reference numeral 25 denotes a similarity comparison circuit that compares the degree of similarity between the voice characteristic pattern from the initial storage circuit 23 and the pattern from the pattern storage circuit 24. Based on the result of the comparison, the control signal output circuit 26 outputs the control signal 8. Outputs ~9. Therefore, when the respective outputs of the comparison circuits 17, 18, and 19 are A ₁ , A ₂ , and A ₃ , 8Fi>1.2ΣFi…A ₁ =1 8Fi≦1.2ΣFi…A ₁ =0 8Fi>ΣFi …A ₂ =1 8Fi≦ΣFi…A ₂ =0 8Fi>0.8ΣFi…A ₃ =1 8Fi≦0.8ΣFi…A ₃ =0 are respectively output. On the other hand, the code conversion circuit 22 uses the outputs of the comparison circuits 17, 18, 19, A ₁ ,
It takes A ₂ and A ₃ as input and outputs two outputs B ₁ and B _2. The relationship between A ₁ , A ₂ , A ₃ and B ₁ , B ₂ is A ₁ , A ₂ , A ₃ ...B ₁ ,B ₂ (1,X,X)...(1,1) (0,1,X)...(1,0) (0,0,1)...(0,1) (0,0 ,0)...(0,0). Note that X indicates that it may be either 1 or 0. As described above, the output of the filter 3 is compressed into 2-bit data B ₁ and B ₂ and stored in the initial storage circuit 23 of the audio storage circuit 7. Address control circuit 1 in both the voice registration state and voice recognition state.
6 stores in the initial storage circuit 23 the characteristic pattern data compressed to 2 bits from the beginning to the end of the voice. When the registration state is instructed by the selection switch 21, the address control circuit 16 transfers and stores the characteristic pattern stored in the initial storage circuit 23 in the pattern storage circuit 24 of the area corresponding to the control content. This storage area for registered patterns is sequentially updated every time a voice is registered after the selection switch 21 is operated. Next, when the speech recognition state is instructed by the selection switch 21, the characteristic pattern from the start to the end of the speech is stored in the initial storage circuit 23, as in the previous case. In the case of this recognition, the feature pattern stored in the initial storage circuit 23 is input to the similarity comparison circuit 25. At this time, the compressed 2-bit data of each corresponding filter 3 output value at each corresponding sampling time point of the feature pattern from the similarity comparison circuit 25 and that from the pattern storage circuit 24 are combined into (1, 1). Or if (0,0) then [1], otherwise

[0], calculate the sum for each registered pattern, and output it to the control signal output circuit 26. The control signal output circuit 26 finds the minimum value of the sum and outputs control signals 8 to 9 corresponding to this registered pattern. Let us now consider the specific sound ``ichi'' shown in Figure 2. The filter output values at sampling times t ₁ and t ₂ in FIG. 2 are shown in the table in FIG. 4. FIG. 5 shows the additive average value of each filter output value of FLT ₁ to _{FLT 8} and the threshold value obtained by multiplying this by a constant of 1.2 and 0.8. When the filter output value is F ₀ , Fo＞1.2/8ΣFi…++ 1.2/8Fo＞1/8ΣFi…+− 1/8ΣFi≧Fo＞0.8/8ΣFi…−+ 0.8/8ΣFi >Fo...-- The output values of each filter are computed by the arithmetic circuit 6 to obtain the compressed data shown in FIG. Data compressed to 2 bits by the processing method described above has the following properties. (A) Standardization is being performed for fluctuations in the amplitude direction of audio. In other words, since the relative fluctuations in the frequency spectrum of the voice are extracted even when the voice is uttered loudly or with an accent, a characteristic pattern that nullifies the fluctuation in the amplitude direction of the voice can be obtained. (B) Data compression is performed by comparing the average value multiplied by a constant, so in connection with recognition processing, by extracting only large fluctuations in feature parameters, it is possible to detect small differences in utterances. Disable variation. Due to the properties (A) and (B) above, the data compression according to the present invention provides high recognition performance considering the memory capacity used, and also because the memory capacity used is small. , since the recognition calculation processing time is short, it has the advantage that the recognition calculation processing time is fast. The recognition calculation process for the feature parameters obtained in this way calculates the similarity between the feature pattern/recognition pattern corresponding to the input voice and the feature pattern (registered pattern) corresponding to the generally registered control content. The time value when both the recognition pattern performed by doing this and the compressed data of each corresponding filter at each corresponding sampling point of the registered pattern is ++ or - is [1], and the value less than that is [1].

Find the sum as [0],
A control signal corresponding to the registered pattern with the largest sum obtained is output. Such recognition calculation processing ignores slight fluctuations in each filter output value of the input voice, and allows stable filter outputs to have a large effect on the recognition calculation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the outline of the device of the present invention;
Fig. 2 is a waveform diagram of the envelope voltage for each audio frequency band, Fig. 3 is a block diagram showing the configuration of the main part of the device of the present invention, and Fig. 4 is a table showing the data compression status according to the present invention. , FIG. 5 is a table of threshold values used for data compression, where 3 is a filter, 4 is an A/D, 6 is an arithmetic circuit, 7 is an audio storage circuit, and 11
is an adder circuit, 12 is a delay circuit, 13, 14, 15
is a multiplication circuit, 16 is an address control circuit, 17,1
8 and 19 are comparison circuits, 21 is a selection switch, 22
2 shows a code conversion circuit, 23 an initial storage circuit, 24 a pattern storage circuit, and 25 a similarity comparison circuit, respectively.

Claims (1)

[Claims] 1. A microphone that converts audio into an audio signal, a filter that analyzes the frequency of this audio signal,
It consists of an analog-to-digital conversion circuit that converts the filter output into a digital value, and an arithmetic circuit to which the digitized filter output obtained from this conversion circuit is input, and the arithmetic circuit performs sampling at fixed time intervals. means for calculating a threshold value by multiplying the average value of the filter outputs by a predetermined constant, means for comparing the threshold value with the filter, and means for compressing data based on the comparison result; The device is characterized by being configured by means for performing a recognition operation between compressed data and pre-stored audio compression data, and means for outputting a control signal corresponding to the voice specified by the recognition operation. voice recognition device.