JPS6149417A - Forming method of buried layer - Google Patents
Forming method of buried layerInfo
- Publication number
- JPS6149417A JPS6149417A JP59171145A JP17114584A JPS6149417A JP S6149417 A JPS6149417 A JP S6149417A JP 59171145 A JP59171145 A JP 59171145A JP 17114584 A JP17114584 A JP 17114584A JP S6149417 A JPS6149417 A JP S6149417A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- buried layer
- glass
- pattern
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
- H10P32/141—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer comprising oxides only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
- H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は周辺部へのドーパントのオートトープを防止し
た埋没層の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for forming a buried layer that prevents autotope of a dopant from entering the peripheral area.
バイポーラICの形成工程においては各半導体素子のコ
レクタの直列抵抗を少なくするために半導体基板(以下
略して基板)に埋没層の形成が行われている。In the process of forming a bipolar IC, a buried layer is formed in a semiconductor substrate (hereinafter simply referred to as a substrate) in order to reduce the series resistance of the collector of each semiconductor element.
ここで埋没層は基板とは異種の導電型で高い伝導度を示
す半導体領域からなり、この上に半導体のエピクキシャ
ル成長を行い、引き続いてドーパントの拡散或いは注入
が行われる段階でコレクク領域との接続が行われている
。Here, the buried layer consists of a semiconductor region that is of a different conductivity type than the substrate and exhibits high conductivity, and the semiconductor is epitaxially grown on this layer, and then connected to the collector region during the subsequent diffusion or implantation of dopants. is being carried out.
ここでICを構成する各素子は基板内部の半導体領域で
は完全に絶縁されていることが必要でこれを達成するた
め拡散接合分離或いは誘電体分離が行われている。Each element constituting the IC needs to be completely insulated in the semiconductor region inside the substrate, and to achieve this, diffusion junction isolation or dielectric isolation is performed.
然し、最初に行われる埋没層の形成工程においてパター
ン形成領域以外にもドーパントがオートドープして拡が
っており、これにより埋没層が実質的に拡大して設けら
れていると、素子間分離が充分に行われず、場合によっ
ては短絡状態が生じ、これがIC形成に当たって収率低
下の原因となっている。However, in the first buried layer formation process, the dopant is autodoped and spread beyond the pattern formation area, and if the buried layer is substantially enlarged as a result, the isolation between elements may not be sufficient. In some cases, a short-circuit condition occurs, which causes a decrease in yield when forming an IC.
そのためドーパントのオートドープか生じない埋没層の
形成方法が要望されている。Therefore, there is a need for a method for forming a buried layer that does not cause autodoping of dopants.
埋没層の形成方法には各種の方法が実用化されている。 Various methods have been put into practical use for forming the buried layer.
例えば基板上に化学気相成長法(略称CVD法)或いは
熱酸化法により二酸化珪素(SI02)層を形成し、こ
れに写真食刻技術(ホトリソグラフィ)を用いて埋没層
形成領域の窓開けを行った後、この窓開は部にイ1ン注
入を行うか、或いはこの窓開は部を含めてこの上にスピ
ンコード法を用いてドーパントを含んだ珪酸塩ガラス(
シリケートガラス)を塗布して薄膜を作り、これを熱処
理してシリケートガラス中に含まれているドーパントを
拡散させて形成する方法がある。For example, a silicon dioxide (SI02) layer is formed on a substrate by a chemical vapor deposition method (abbreviated as CVD method) or a thermal oxidation method, and then a window is opened in the buried layer formation region using photolithography. After this process, the aperture is either implanted into the part, or a dopant-containing silicate glass (silicate glass (
There is a method in which a thin film is formed by applying silicate glass (silicate glass), and this is heat-treated to diffuse the dopant contained in the silicate glass.
また、基板上に直接ドーパントを含んだシリケートガラ
スをスピンコードして拡散源となる薄膜を作り、これに
写真食刻技術を用いてパターンニングし、その後に薄膜
中の不純物を熱拡散させて埋没層を作る方法もある。In addition, we spin-code silicate glass containing dopants directly onto the substrate to create a thin film that serves as a diffusion source, pattern this using photolithography, and then thermally diffuse the impurities in the thin film and embed it. Another method is to create layers.
ここで、これらの方法を比較すると工程的には後者の方
法が最も簡単であり、基板上にスピンコード法でシリケ
ートガラス層を形成する方法はスピン・オン・グラス法
と言われ一般に使用されている。Comparing these methods, the latter method is the simplest in terms of process, and the method of forming a silicate glass layer on a substrate by spin coding is called the spin-on-glass method and is generally used. There is.
本発明はこの方法により埋没層を形成する方法の改良に
関するものである。The present invention relates to an improvement in the method of forming a buried layer using this method.
第2図(A)〜(D)は従来の埋没層形成工程を示す断
面図である。FIGS. 2A to 2D are cross-sectional views showing a conventional buried layer forming process.
すなわち、基板1の上にアルコールなどの溶剤を用いて
粘度調節したゲル状のドーパント添加のシリケートガラ
ス(例えばアンチモン添加のシリケートガラス、以下略
してsbガラス)をスピンコード法を用いて被覆した後
、約200℃の温度で加熱して溶剤及びバインダなどを
蒸発或いは分解せしめ、同図(A)に示すように約15
00人の厚さのsbガラス層2を形成する。That is, after coating a gel-like dopant-added silicate glass (for example, antimony-added silicate glass, hereinafter abbreviated as sb glass) whose viscosity is adjusted using a solvent such as alcohol on the substrate 1 using a spin cord method, The solvent, binder, etc. are evaporated or decomposed by heating at a temperature of about 200°C, and as shown in Figure (A), about 15
An sb glass layer 2 having a thickness of 0.00 mm is formed.
次に写真食刻技術を用いてホトエツチングを行い1、同
図(B)に示すようにsbガラスからなる埋没層パター
ン3を形成する。Next, photoetching is performed using a photolithographic technique 1 to form a buried layer pattern 3 made of SB glass, as shown in FIG. 3(B).
次に埋没層パターン3を形成した基板1の上にCVD法
を用いて全面にSi 02層4を形成し、同図(C)に
示すように被覆するが、このCVD処理温度は800〜
850℃と高いために、この工程中に埋設層パターン3
の表面からアンチモン酸化物(Sb 205’、 S
b 203 )の蒸発が起こり、パターンの周辺にこれ
らの酸化物が再イ」着する所謂オートドープが起こり易
い。Next, a Si02 layer 4 is formed on the entire surface of the substrate 1 on which the buried layer pattern 3 has been formed using the CVD method, and is coated as shown in FIG.
Because the temperature is as high as 850°C, the buried layer pattern 3 is removed during this process.
Antimony oxide (Sb 205', S
b 203 ) evaporates and these oxides are likely to re-deposit around the pattern, so-called autodoping.
こ\で、埋没層パターン3の上をS i Oz 層4で
覆う理由は次に行うドーパントの拡散工程においてドー
パントであるsbの拡散を埋没層ノ〈ターン領域のみに
限定したいためである。The reason why the buried layer pattern 3 is covered with the SiOz layer 4 is that in the next dopant diffusion step, it is desired to limit the diffusion of the dopant sb only to the turn region of the buried layer.
然し、先に説明したように埋没層パターン3の周辺にs
bが存在していると、1200〜1250°Cで行われ
る拡散処理において同図(’D )に示すように埋没層
パターン3が存在する基板1の中にsb拡散層6ができ
るだけでなく、周辺部7にも生じてしまい、これが原因
して後で素子間分離を行っても絶縁不良あるいは導通と
云うIC不良を起こしていた。However, as explained earlier, there is s around the buried layer pattern 3.
When b is present, in the diffusion treatment performed at 1200 to 1250°C, not only is an sb diffusion layer 6 formed in the substrate 1 where the buried layer pattern 3 is present, as shown in FIG. This also occurs in the peripheral area 7, and this causes IC failures such as insulation failure or conduction even if elements are isolated later.
以上説明したようにスピン・オン・グラス法を用いて基
板に埋没層を形成する工程においてドーパントが埋没層
パターンの周辺にまで拡散するオート・ドープ現象が起
こり、それによってICの素子間分離が充分に達成され
ないことが問題である。As explained above, in the process of forming a buried layer on a substrate using the spin-on-glass method, an auto-doping phenomenon occurs in which dopants diffuse to the periphery of the buried layer pattern, thereby ensuring sufficient isolation between IC elements. The problem is that it is not achieved.
上記問題点は半導体基板上にsbガラス層と5402層
とを順次形成した後、選択工・ノチングを行って二層構
造の埋没層パターンを形成し、更に再びSt 02層
を全面に被覆した後に熱処理を行い、前記sbガラス中
のsbを半導体基板上に拡散させる埋没層の形成方法を
とることにより解決することができる。The above problem can be solved by sequentially forming the SB glass layer and the 5402 layer on the semiconductor substrate, performing selective processing and notching to form a two-layer buried layer pattern, and then covering the entire surface with the St 02 layer again. This problem can be solved by using a method of forming a buried layer in which the sb in the sb glass is diffused onto the semiconductor substrate by heat treatment.
本発明は埋没層パターン周辺へのドーパントの拡散はこ
の上にSi 02層を被覆するCVD処理工程中にs
bガラス層からのオートドープによって生ずるものであ
るが、このCVD処理温度では埋没層パターンから基板
へのドーパントの拡散は無視できる程少ない点に着目し
、埋没層ノ々ターン形成前にSbカラス層の上にSi
02層を薄く設けておくことによってCVD処理工程
中にドーノマントのオートドープが生ずるのを抑制する
ものである。In the present invention, dopant diffusion to the periphery of the buried layer pattern is achieved during the CVD process of coating the Si02 layer on top of the dopant.
This is caused by autodoping from the B glass layer, but we focused on the fact that the diffusion of dopants from the buried layer pattern to the substrate is negligible at this CVD processing temperature, and the Sb glass layer is on top of Si
By providing the 02 layer thinly, autodoping of the donomant is suppressed from occurring during the CVD process.
第1図(A)〜(D)は本発明に係る処理工程を示す断
面図である。FIGS. 1A to 1D are cross-sectional views showing processing steps according to the present invention.
すなわち同図(A)に示すように基板1の上に従来と同
様にスピン・オン・グラス法でsbガラス層2を約15
00人の厚さに形成した後、引き続いてC、V D法に
よりこの上に約1000への厚さにSi02層8を形成
する。That is, as shown in the same figure (A), approximately 15 sb glass layer 2 is deposited on the substrate 1 by the spin-on-glass method as in the conventional method.
After forming the SiO2 layer 8 to a thickness of approximately 1000 nm, a SiO2 layer 8 is subsequently formed thereon to a thickness of approximately 1000 nm using the C, VD method.
ここで、CVD処理温度は800〜850°Cであるが
この程度の温度ではsbガラス層2から基板1へのドー
パントの拡散は生じない。Here, the CVD processing temperature is 800 to 850°C, but at this temperature, dopant does not diffuse from the sb glass layer 2 to the substrate 1.
次に同図(B)に示すように写真食刻法を用いて二層構
造の埋没層パターン9を形成する。Next, as shown in FIG. 2B, a buried layer pattern 9 having a two-layer structure is formed using photolithography.
この工程では殆ど熱は加わらないので、基板1の表面に
ドーパントが付着することはない。Since almost no heat is applied in this step, no dopant adheres to the surface of the substrate 1.
次に従来と同様にCVD法を用い、同図(C)に示すよ
うにSi 02層4の形成を行う。Next, as in the conventional method, a CVD method is used to form a Si 02 layer 4 as shown in FIG. 2(C).
グ ここでsbガラス層2の端面は露出し
ているが露出面積が微少であることから周辺領域へのオ
ートドーピングは従来に較べて桁違いに少ない。Here, the end face of the sb glass layer 2 is exposed, but since the exposed area is minute, autodoping to the peripheral region is much less than in the past.
次に同図(D)に示すように従来と同様に1200〜1
250℃で拡散処理を行うと、sbガラス層2がある埋
没層パターン9からのみドーパントであるsbの拡散が
行われ、理想的な埋没層10を形成することができる。Next, as shown in the same figure (D), 1200 to 1
When the diffusion treatment is performed at 250° C., the dopant sb is diffused only from the buried layer pattern 9 where the sb glass layer 2 is located, and an ideal buried layer 10 can be formed.
以上のように本発明の実施により埋没層パターンをCV
D法を用いてSt 02層で被覆する段階でのドーパ
ントによる周辺部の汚染を抑制することができ、従って
埋没層形成工程での収率の向上が可能となる。As described above, by implementing the present invention, the buried layer pattern can be
It is possible to suppress contamination of the peripheral area due to dopants during the step of covering with the St 02 layer using the D method, and therefore it is possible to improve the yield in the buried layer forming process.
第1図(A)〜(D)は本発明を実施した埋没層の形成
工程を示す断面図、
第2図(A)〜(D)は従来法による埋没層の形成工程
を示す断面図、
である。
図において−
1は基板、 2はsbガラス層、3.9
は埋没層パターン、4,8むよSi Oz層、5はs
b、 6はsb拡11ダ層、7は周辺部、
10は埋没層、である。FIGS. 1(A) to (D) are cross-sectional views showing the process of forming a buried layer according to the present invention; FIGS. 2(A) to (D) are cross-sectional views showing the process of forming a buried layer using a conventional method; It is. In the figure - 1 is the substrate, 2 is the sb glass layer, 3.9
is a buried layer pattern, 4, 8 is a SiOz layer, 5 is a s
b, 6 is the sb expansion layer, 7 is the peripheral area,
10 is a buried layer.
Claims (1)
順次形成した後、選択エッチングを行って二層構造の拡
散源パターンを形成し、しかる後二酸化珪素層を全面に
被覆した後に熱処理を行い、前記アンチモンガラス中の
アンチモンを半導体基板中に拡散させて埋没層を形成す
ることを特徴とする埋没層の形成方法。After sequentially forming an antimony glass layer and a silicon dioxide layer on a semiconductor substrate, selective etching is performed to form a two-layer structure diffusion source pattern, and after that, the entire surface is covered with a silicon dioxide layer, and then heat treatment is performed. A method for forming a buried layer, which comprises forming a buried layer by diffusing antimony in antimony glass into a semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59171145A JPS6149417A (en) | 1984-08-17 | 1984-08-17 | Forming method of buried layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59171145A JPS6149417A (en) | 1984-08-17 | 1984-08-17 | Forming method of buried layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6149417A true JPS6149417A (en) | 1986-03-11 |
Family
ID=15917817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59171145A Pending JPS6149417A (en) | 1984-08-17 | 1984-08-17 | Forming method of buried layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6149417A (en) |
-
1984
- 1984-08-17 JP JP59171145A patent/JPS6149417A/en active Pending
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