JPS6149452A - Semiconductor element - Google Patents
Semiconductor elementInfo
- Publication number
- JPS6149452A JPS6149452A JP59171871A JP17187184A JPS6149452A JP S6149452 A JPS6149452 A JP S6149452A JP 59171871 A JP59171871 A JP 59171871A JP 17187184 A JP17187184 A JP 17187184A JP S6149452 A JPS6149452 A JP S6149452A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- electrode
- semiconductor device
- semiconductor element
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/934—Cross-sectional shape, i.e. in side view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/981—Auxiliary members, e.g. spacers
- H10W72/983—Reinforcing structures, e.g. collars
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はIC,LSI等の半導体素子に係り、とくにそ
の電極構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to semiconductor devices such as ICs and LSIs, and particularly relates to their electrode structures.
従来例の構成とその問題点 半導体素子は半導体基板表面にトランジスタ。Conventional configuration and its problems The semiconductor element is a transistor on the surface of a semiconductor substrate.
抵抗、ダイオード等の回路要素を形成し、Al等の導体
層で相互に配線して所期の回路を形成した後、一度全面
に絶縁膜でおおい、ついで絶縁膜の一部を除去してその
開口部に導体層の一部を露出させ、後の工程で素子と外
部回路もしくはリードとの電気的接続を行なうための素
子側電極(ボンディングパッド)とする。After forming circuit elements such as resistors and diodes and interconnecting them with a conductive layer such as Al to form the desired circuit, the entire surface is covered with an insulating film, and then a part of the insulating film is removed to form the desired circuit. A portion of the conductor layer is exposed in the opening and serves as an element-side electrode (bonding pad) for electrically connecting the element to an external circuit or lead in a later step.
この最上層の絶縁膜は表面保護膜と呼ばれ、以後の工程
で不意に加えられた外力から素子を保護したシ、外部か
ら水分や不純物が侵入して配線導体を腐食したり、さら
に下層の回路要部に到達して機能がそこなわれるのを防
止するだめのものである。この絶縁膜を成長させる反応
方式と材料としては第1に、プラズマ反応を併用したC
VD(P−CVD)法にヨルシリコン窒化物、8102
゜両者を比較すると前者のP−CVD法による膜は膜質
が緻密でステップカバレージ(段差被着性)も良好であ
シ比較的うすい膜でもすぐれた機械的強度と耐湿性を示
すが、一般に膜成長速度が小さく、加えて処理がバッチ
方式となるため量産性に乏しい。This top layer insulating film is called a surface protection film, and protects the device from external forces unexpectedly applied in subsequent processes. This is to prevent it from reaching the main parts of the circuit and damaging its function. The first reaction method and material for growing this insulating film are C
Yorosilicon nitride, 8102 for VD (P-CVD) method
゜Comparing the two, the former P-CVD film has a dense film quality and good step coverage (step adhesion), and even a relatively thin film shows excellent mechanical strength and moisture resistance. The growth rate is slow and the process is batch-based, making it difficult to mass-produce.
一方後者のCvD法K ヨルS z 02−!!タハP
S Gあるいはこれらを組み合わせた膜は量産性はす
ぐれているがP−CVD法による膜はど膜質が緻密では
なくステップカバレージも劣るため十分な機械的強度と
耐湿性を実現するためにはP−CVD法による膜の場合
よシも大きな膜厚を必要とする。On the other hand, the latter CvD method K Yoru S z 02-! ! Taha P
SG or a film made from a combination of these is excellent in mass production, but the film made by the P-CVD method is not dense and has poor step coverage, so in order to achieve sufficient mechanical strength and moisture resistance, it is necessary to use P-CVD. In the case of a film formed by the CVD method, a large film thickness is also required.
経験によれば、たとえば、厚さ0.8〜1.0μmの、
fP −CV D法による膜と同等の耐湿性を得るため
には、S z 02とPSGを用いた膜では1.6μm
以上望ましくは2.0μm以上の膜厚が必要であった。According to experience, for example, with a thickness of 0.8 to 1.0 μm,
In order to obtain the same moisture resistance as a film made by the fP-CVD method, a film using S z 02 and PSG must have a thickness of 1.6 μm.
As described above, a film thickness of preferably 2.0 μm or more was required.
ところがそのような厚い絶縁膜は成長時に下地との熱膨
張係数の差から生じる応力が大きいため亀裂が入りやす
い。特に絶縁膜と大きく異なる熱膨張係数をもつAl等
の導体層と接する部分で亀裂が発生しやすく、またその
連続接触面積が大きいほど発生しやすい。実際の素子で
このような現象が最も発生しやすいのは通常−辺90〜
120μmの方形で設けられる素子電極部(ボンディン
グバンド)である。間部での典型的な亀裂の状態を第1
図と第2図(断面図)に示す。Al等でなる素子電極部
1の周縁部で表面絶縁膜2に亀裂が入り、数カ所から周
囲に向かっても伝播している。電極部上のほとんど(破
線6で囲まれた領域)の表面絶縁膜は後工程で除去され
るが周囲に伸びた亀裂はそのまま残され、水分や不純物
が容易に侵入するため信頼性上の大きな問題となる。以
上の理由から従来の構成では十分に厚いCVD法による
絶縁膜を設けることが困難であった。However, such a thick insulating film is prone to cracking because of the large stress generated from the difference in thermal expansion coefficient with the underlying layer during growth. In particular, cracks are likely to occur in areas where they come into contact with conductive layers such as Al, which have a coefficient of thermal expansion significantly different from that of the insulating film, and the larger the continuous contact area, the more likely they are to occur. In actual devices, this phenomenon is most likely to occur on sides of 90~
This is an element electrode portion (bonding band) provided in a rectangular shape of 120 μm. The first example is the typical crack condition in the gap.
and FIG. 2 (cross-sectional view). Cracks appear in the surface insulating film 2 at the periphery of the element electrode portion 1 made of Al or the like, and the cracks also propagate toward the periphery from several locations. Although most of the surface insulating film on the electrode part (area surrounded by broken line 6) is removed in a later process, the cracks that extend around the electrode remain as they are, allowing moisture and impurities to easily penetrate, which poses a significant problem in terms of reliability. It becomes a problem. For the above reasons, it has been difficult to provide a sufficiently thick insulating film using the CVD method in the conventional structure.
発明の目的
本発明は従来の欠点を解消し、十分厚い表面保護膜を亀
裂の発生をともなわずに設けることができる半導体素子
を提供することを目的としている。OBJECTS OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art and to provide a semiconductor element in which a sufficiently thick surface protective film can be provided without causing cracks.
発明の構成
本発明はボンディングパッドを含む配線パターンをなす
導体層とすぐ上に形成された絶縁膜を有する半導体素子
で、ボンディングパッドが複数に分割されていることを
特徴とする半導体素子であって、これによシボンディン
グパッドをなす導体と絶縁膜との連続接触面積が小さく
なシ絶縁膜成長時に絶縁膜に亀裂が入ることが防止でき
る。Structure of the Invention The present invention is a semiconductor element having a conductor layer forming a wiring pattern including a bonding pad and an insulating film formed immediately above the semiconductor element, wherein the bonding pad is divided into a plurality of parts. This makes it possible to prevent cracks from forming in the insulating film during growth of the insulating film in which the continuous contact area between the conductor forming the bonding pad and the insulating film is small.
実施例の説明
以下図面を参照しながら本発明の詳細な説明する。第3
図および第4図は本発明による半導体素子の電極構造を
示す平面図および断面図である。DESCRIPTION OF EMBODIMENTS The present invention will now be described in detail with reference to the drawings. Third
FIG. 4 is a plan view and a cross-sectional view showing the electrode structure of a semiconductor device according to the present invention.
−辺40〜60μmの方形のAlもしくはAlを主成分
とする合金等の導体層1が4つの分割面でひとつの電極
部を形成している。相互の間隔は5〜16μmが適轟で
ある。この構造は従来の電極部を、その中央付近で交差
する2本の6〜15μm幅の溝で分割したものと同等で
、製造工程上は導体配線パターン形成用のマスクに若干
の変更を加えることにより容易に実行でき、新たな素子
加工工程は何ら必要としない。- A rectangular conductor layer 1 made of Al or an alloy containing Al as a main component and having sides of 40 to 60 μm forms one electrode portion with four divided planes. A suitable distance between them is 5 to 16 μm. This structure is equivalent to a conventional electrode part divided by two 6-15 μm wide grooves that intersect near the center, and the manufacturing process requires slight changes to the mask for forming the conductor wiring pattern. This can be easily carried out by the method, and no new device processing steps are required.
電極部をこのような構造にすることにより電極を構成す
るAl等の導体金属とS x 02あるいはPSG等の
絶縁膜との連続接触面積は約−となる。By making the electrode part have such a structure, the continuous contact area between the conductive metal such as Al constituting the electrode and the insulating film such as S x 02 or PSG becomes approximately -.
これによってたとえば2.0〜2.5μmの厚みのCV
D法によるSio2あるいはPSGからなる絶縁膜を成
長させても亀裂を生ずることはなかった。By this, for example, a CV with a thickness of 2.0 to 2.5 μm
Even when an insulating film made of Sio2 or PSG was grown using the D method, no cracks were generated.
なお溝の部分では表面絶縁膜に開口部を設けた際、下地
が露出するが、その面積は電極部全体に比してわずかで
あり、従来同様にたとえばAuある−いはA/=の細線
によってボールボンドを実施すれば、第5図に示すよう
な接合がなされ、はとんどの接合面が細線材料であるA
uまたはAlと、電極材料であるAlまたはAl合金と
の接合となるため電気的1機械的に何ら問題はない。Note that when an opening is made in the surface insulating film in the groove part, the base is exposed, but the area is small compared to the entire electrode part, and as in the past, for example, a thin wire of Au or A/= is exposed. If ball bonding is carried out, a bond as shown in Fig. 5 will be made, and most of the bonding surfaces will be made of thin wire material.
There is no problem electrically or mechanically because the bond is between u or Al and Al or Al alloy which is the electrode material.
発明の効果
以上述べたように本発明によれば、CVD法によるSi
OまたはPSG等の絶縁膜を従来よシも厚く設けること
が可能となシ、量産性にすぐれかつ高信頼性の半導体素
子が実現される。Effects of the Invention As described above, according to the present invention, Si
It is possible to provide an insulating film such as O or PSG thicker than in the past, and a highly reliable semiconductor element that is highly mass-producible can be realized.
第1図および第2図は従来の半導体素子における電極部
と電極部周辺の表面絶縁膜の状態を示す要部平面図と断
面図、第3図および第4図は本発明による半導体素子の
電極部構造と表面絶縁膜の状態を示す要部平面図および
断面図、第5図は本発明による半導体素子の電極部にポ
ールボンドで金属細線を接続した状態を示す要部断面図
である。
1・・・・・・素子電極部(ボンディングパッド)、2
・・・・・・表面絶縁膜、3・・・・・・亀裂、4・・
・・・・下地、6・・・・・・絶縁膜開口部、6・・・
・・・金属細線端。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図
第2図
第3図
第4図1 and 2 are main part plan views and cross-sectional views showing the state of the electrode portion and the surface insulating film around the electrode portion in a conventional semiconductor device, and FIG. 3 and 4 are electrodes of a semiconductor device according to the present invention. FIG. 5 is a plan view and a cross-sectional view of a main part showing the structure and state of a surface insulating film, and FIG. 5 is a cross-sectional view of a main part showing a state in which thin metal wires are connected to electrode parts of a semiconductor element according to the present invention by pole bonding. 1...Element electrode part (bonding pad), 2
...Surface insulating film, 3...Crack, 4...
... Base, 6 ... Insulating film opening, 6 ...
...Thin metal wire end. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4
Claims (5)
体層と、同導体層の一部直上に形成された絶縁膜とを有
する半導体素子で、前記ボンディングパッドが複数に分
割されていることを特徴とする半導体素子。(1) A semiconductor element having a conductor layer forming a wiring pattern including a bonding pad and an insulating film formed directly above a portion of the conductor layer, characterized in that the bonding pad is divided into a plurality of parts. semiconductor element.
本の溝によって4分割されている特許請求の範囲第1項
に記載の半導体素子。(2) The bonding pads intersect near the center 2
The semiconductor device according to claim 1, which is divided into four parts by a book groove.
ある特許請求の範囲第1項あるいは第2項に記載の半導
体素子。(3) The semiconductor device according to claim 1 or 2, wherein the conductor layer is made of Al or an alloy containing Al as a main component.
ilicateglass)から選ばれてなる特許請求
の範囲第1項に記載の半導体素子。(4) The insulating film is SiO_2, PSG (Phosphos)
2. The semiconductor device according to claim 1, which is selected from the group consisting of ilicate glass.
第4項に記載の半導体素子。(5) The semiconductor device according to claim 4, wherein the insulating film has a thickness of 2 μm or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59171871A JPS6149452A (en) | 1984-08-17 | 1984-08-17 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59171871A JPS6149452A (en) | 1984-08-17 | 1984-08-17 | Semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6149452A true JPS6149452A (en) | 1986-03-11 |
Family
ID=15931335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59171871A Pending JPS6149452A (en) | 1984-08-17 | 1984-08-17 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6149452A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4742106A (en) * | 1986-02-03 | 1988-05-03 | Nippon Petrochemicals Company, Limited | Polyolefin compositions having high rigidity and high impact resistance |
| US4764546A (en) * | 1986-04-25 | 1988-08-16 | Sumitomo Chemical Co., Ltd. | Filler-containing polypropylene resin composition and process for producing the same |
| WO2002001637A3 (en) * | 2000-06-28 | 2002-09-26 | Intel Corp | Layout and process for a device with segmented ball limited metallurgy for the inputs and outputs |
| US7180195B2 (en) | 2003-12-17 | 2007-02-20 | Intel Corporation | Method and apparatus for improved power routing |
| US20100314734A1 (en) * | 2009-06-14 | 2010-12-16 | Terepac | Processes and structures for IC fabrication |
| WO2014162386A1 (en) * | 2013-04-01 | 2014-10-09 | パイオニア株式会社 | Wire connection structure and electrical device |
-
1984
- 1984-08-17 JP JP59171871A patent/JPS6149452A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4742106A (en) * | 1986-02-03 | 1988-05-03 | Nippon Petrochemicals Company, Limited | Polyolefin compositions having high rigidity and high impact resistance |
| US4764546A (en) * | 1986-04-25 | 1988-08-16 | Sumitomo Chemical Co., Ltd. | Filler-containing polypropylene resin composition and process for producing the same |
| WO2002001637A3 (en) * | 2000-06-28 | 2002-09-26 | Intel Corp | Layout and process for a device with segmented ball limited metallurgy for the inputs and outputs |
| US7034402B1 (en) | 2000-06-28 | 2006-04-25 | Intel Corporation | Device with segmented ball limiting metallurgy |
| US7033923B2 (en) | 2000-06-28 | 2006-04-25 | Intel Corporation | Method of forming segmented ball limiting metallurgy |
| US7180195B2 (en) | 2003-12-17 | 2007-02-20 | Intel Corporation | Method and apparatus for improved power routing |
| US7208402B2 (en) | 2003-12-17 | 2007-04-24 | Intel Corporation | Method and apparatus for improved power routing |
| US20100314734A1 (en) * | 2009-06-14 | 2010-12-16 | Terepac | Processes and structures for IC fabrication |
| US8759713B2 (en) * | 2009-06-14 | 2014-06-24 | Terepac Corporation | Methods for interconnecting bonding pads between components |
| WO2014162386A1 (en) * | 2013-04-01 | 2014-10-09 | パイオニア株式会社 | Wire connection structure and electrical device |
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