JPS6150335B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital multiplication circuit, and relates to a multiplier used in digital signal processing equipment such as PCM that changes the level and frequency characteristics of a digital signal. To provide a digital multiplication circuit which can perform multiplication processing by double precision arithmetic even if the number of bits of input data to be processed is larger than the number of bits of a multiplier.

Generally, a digital multiplier is required when attenuating the level or changing the frequency characteristics of a PCM digital signal. However, if the number of bits in the multiplier is smaller than the number of bits in the multiplier input data or any coefficient that is the multiplicand, the calculation must be performed by dividing.

On the other hand, PCM digital signals are usually handled in two's complement representation. When such two's complement data is divided and calculated as described above, the division calculation is impossible if the input data of the multiplier or the coefficient of the multiplicand is negative. For example, if the input signal is 8 bits,
Consider performing multiplication with a 4-bit coefficient using two 4-bit multipliers.

In other words, if the input signal is 0.1011101 and the coefficient is 1.010, the answer in normal 8-bit calculation is
11.0111010010, but if you divide this into 4 bits and calculate, the first 4 bits are 0101×1010
=11100010 and the next 4 bits are 1101×1010=
00010010 and the result of adding these is
11.1000110010, which is completely different from the true answer. For this reason, conventionally, as shown in FIG. 1, input data input to terminal 1 and held in holder 2 and coefficients output from coefficient unit 4 are converted into binary codes in converters 3 and 5, respectively. and is supplied to the multiplier 6. The multiplied result in the multiplier 6 must be converted into two's complement representation from the offset binary code in the converter 10 and output. For this reason,
There were disadvantages such as the need for converters 3, 5, and 10, and the long calculation time.

The present invention eliminates the above-mentioned drawbacks, and a specific embodiment thereof will be described with reference to FIG. 2.

In this embodiment, it is assumed that a 4-bit x 4-bit multiplier is used, the input data of the multiplier is 8 bits, and the coefficient of the multiplicand is 4 bits. That is, assume that the input data is 0.1011101, the coefficient is 1.010, and is expressed as a two's complement number, and that this multiplication is performed using a 4×4 bit multiplier.

First, input data input to the terminal 11 is held in input holders 12 and 13 as a 4-bit signal sequence, respectively. That is, the upper 4 bits of 0.101 are input to the input holder 12, and the lower 4 bits of 1101 are input to the input holder 13.

Output of upper 4 bits from input holder 12 is 0.101
and the coefficient 1.010 from the coefficient unit 4 are multiplied by the multiplier 6 to obtain 1.100010, which is supplied to the holder 7.

On the other hand, the output of the lower 4 bits from the input holder 13
1101 is supplied to the signal processor 14. The signal processor 14 multiplies the lower 4-bit signal by 1/2. That is, the output signal is shifted down one bit at a time.
A 0 is placed in the MSB, resulting in 0110. Multiplier 6
multiplies this 0110 by the coefficient 1.010, and this result is
11.011100 is supplied to the holder 8. The output of the holder 8 is supplied to a signal processor 15. The signal processor 15 first doubles the 8-bit data of the multiplication result. That is, 11.011100 is doubled,
10.111000. Here, this data is shifted 4 bits to the right for digit alignment with the operation result of the upper bits stored in the holder 7. generally 8
Divide the bit x 8 bit multiplication to 4 bit x 4
When executing in bits, if a negative number is included in the multiplicand in two's complement representation, the two's complement representation processing during the calculation will result in a 4-bit x 4-bit operation result and an 8-bit x 8-bit operation result. A fundamental error occurs between the two. Therefore, when shifting 4 bits to the right, if the MSB is a negative number, a negative number is similarly added to the upper part to make 12 bits of 111110111000. Here, shifting the operation result of the lower bits by a predetermined bit amount for digit alignment with the operation result of the upper bits means shifting it 4 bits to the right using the method described above.
This 12-bit output data and the output data of the holder 7 are added by an adder 9, and the result is
11.0111011000 is obtained and output. Although there is some difference between this result and the true value 11.0111010010, it is 1.0111011 in the case of an adder that outputs 8 bits, and the LSB differs by 1 bit. That is, the probability is that a 1/2 LSB difference will occur. This error is
By adding a signal processor, the accuracy can be further increased and reduced.

In the above embodiment, the input signal data is divided,
Although signal processing was performed on the lower bits, the coefficient data may be similarly divided and processed. Furthermore, by increasing the number of holders, multiplication processing can be performed with any number of bits, not just 8 bits as in the embodiment.

As described above, in this embodiment, the PCM digital signal can be multiplied in two's complement representation, and the multiplier can be configured by simply changing the wiring of the input/output holder, and the calculation time can be shortened.

As described above, the digital multiplication circuit according to the present invention multiplies a digital signal expressed as a two's complement by a predetermined coefficient.
A holding circuit that divides and holds the digital signal into an upper signal bit series and a lower signal bit series, and a holding circuit that shifts the lower signal bit series to the right by at least 1 bit and inserts 0 into the most significant bit. a multiplication circuit that multiplies the output bits from the first signal processing circuit and the upper bit series by the coefficient; and a multiplication circuit that multiplies the output bits from the first signal processing circuit by a second signal for obtaining a lower operation result by shifting the 1-bit shift result by a predetermined bit such that the 1-bit shift result matches the multiplication result of the upper bit series in digits; It consists of a processing circuit and an addition circuit that adds the lower-order operation result from the second signal processing circuit and the multiplication result of the upper bit series to obtain the multiplication result, so that it can be directly displayed in two's complement. It is possible to perform multiplication as is, and the multiplier can be configured by simply changing the wiring of the input and output holder outputs. The circuit configuration is simple, the calculation time can be significantly shortened, and calculation errors do not occur. This feature is obtained. Furthermore, similar features can be obtained even if the above processing is applied to the coefficient side and the input digital signal is passed through as is.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional embodiment, and FIG. 2 is a circuit diagram of an embodiment of a digital multiplier according to the present invention. 2, 7, 8, 12, 13...retainer, 3, 5,
10... converter, 6... multiplier, 9... adder,
14, 15...Signal processor.

Claims (1)

[Claims] 1. In a digital multiplication circuit that multiplies a digital signal expressed as a two's complement by a predetermined coefficient,
A holding circuit that divides and holds the digital signal into an upper signal bit series and a lower signal bit series, and shifts the lower signal bit series to the right by at least 1 bit and inserts 0 into the most significant bit. 1st
a signal processing circuit, a multiplication circuit that multiplies the output bits from the first signal processing circuit and the upper bit series by the coefficient, and a multiplication result of the output bits from the first signal processing circuit to the left. a second signal processing circuit that shifts bit by bit and shifts the 1-bit shift result by a predetermined bit such that the 1-bit shift result matches the digit of the multiplication result of the upper bit series to obtain a lower-order operation result; and an addition circuit that adds the lower-order operation result from the second signal processing circuit and the multiplication result of the upper bit series to obtain the multiplication result.