JPS6152019B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a wheel rotation speed calculation circuit, and more particularly to a wheel rotation speed calculation circuit that is optimally applied to anti-skid control of a vehicle. Recently, various anti-skid control devices have been developed as braking devices to provide more effective and safe braking to automobiles on any road surface. In each of these anti-skid control devices, the rotational state or skid state of the wheel is calculated, and the brake fluid pressure transmitted to the wheel cylinder of the wheel brake device is controlled according to this result. Alternatively, in calculating the skid state, the wheel rotation speed, that is, the wheel speed is required. For example, in calculating the rotational state, deceleration is calculated from the wheel speed, and in calculating the skid state, an approximate vehicle speed is calculated from the wheel speed, and the slip rate is calculated from these results. The wheel deceleration is compared to a predetermined deceleration reference value, the wheel slip rate is compared to a predetermined slip rate, and
The brake fluid pressure is controlled based on these results, but the basis of control is the wheel speed in any case. Recent anti-skid control tends to be digitally controlled, but in order to obtain the wheel speed mentioned above, the output from the wheel rotation speed sensor installed on the wheel is converted into a pulse train, and the wheel speed is calculated based on this pulse train. . In other words, the frequency of this pulse train is proportional to the wheel rotation speed, but conventionally, the pulses of this pulse train during a certain period of time are counted, or high-frequency pulses are calculated between the pulses of the pulse train, that is, the wheel rotation at that time. The wheel speed was calculated by counting at a period inversely proportional to the speed. However, in the former method, in order to increase the accuracy of the wheel speed, the above-mentioned fixed time must be made considerably longer, and the calculation requires a long time. Furthermore, in the latter method, the calculation accuracy differs greatly depending on whether the wheel speed is high or low. Furthermore, both of the above methods required complex circuitry to obtain differential manipulation of the wheel speed, ie, wheel deceleration or acceleration. The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a wheel rotational speed calculation circuit that calculates wheel speed almost instantaneously and that allows differentiation operation to be performed very easily. This object, according to the invention, includes a wheel speed signal generator that generates a wheel speed signal with a frequency proportional to the rotational speed of the wheel, and a wheel speed signal corresponding to the wheel rotational speed based on the wheel speed signal of this wheel speed signal generator. A computing unit that calculates and outputs a digital value, and receives the output of this computing unit and counts a certain high frequency signal, and generates one pulse each time this counted value becomes equal to the output of the computing unit. a first divider; a first calculator that continuously counts pulses generated by the first divider within a cycle of the wheel speed signal or a period related to the cycle; a second divider that receives the output of the counter and counts the high frequency signal and generates one pulse each time the counted value becomes equal to the output of the first counter; a second counter that continuously counts the pulses generated by the divider within the cycle or the period of the wheel speed signal, and the output of the second counter is based on the wheel speed signal. The signal is supplied as a signal to the arithmetic unit, and is compared with the output of the arithmetic unit for the previous cycle or period stored therein, and when different, the output of the arithmetic unit is corrected by this difference. This is achieved by a wheel rotation speed calculation circuit characterized by the following. Hereinafter, details of the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of a wheel rotation speed calculation circuit for anti-skid control of an automobile, which is an embodiment of the present invention. It has functions such as memory function, calculation function, etc. This microcomputer 1 is supplied with a digital input related to a wheel speed pulse, which will be described later, and based on this, calculates and outputs a digital value corresponding to the wheel rotational speed at that time. This output is supplied to the preset input terminals P ₁ , P ₂ . . . _Po of the n-bit first divider 2. It is assumed that the timing of presetting the divider 2 is performed by supplying a timing pulse related to the timing of the operation of the microcomputer 1 to the control terminal, although not shown. The CLK terminal of this first divider 2 is
A high frequency pulse fo as shown in is supplied and counted. One pulse is generated from the Q terminal each time this count value becomes equal to a preset digital value. That is, the first divider 2 generates a pulse train having a frequency obtained by dividing the high frequency o of the pulse fo by a preset digital value. The pulse train from the first divider 2 is supplied to the CLK terminal of a first m-bit counter 3. The number m of bits of this counter 3 is determined by the first divider 2
is larger than the number of bits n. This is because the high frequency o of the pulse fo is designed to be much larger than the digital value corresponding to the wheel rotation speed or the frequency of the wheel speed pulse, which will be described in detail later. The R terminal of the first counter 3 is supplied with a preset wheel speed pulse R as shown in FIG. 2E among the wheel speed pulses. This pulse R clears the count value of the first counter 3. A count value is output from the output terminals O ₁ , O ₂ . . . O _n of the first counter 3, and this is a D-type latch circuit 4
supplied to This latch circuit 4 has m bits like the first counter 3, and the output terminals O ₁ , O ₂ . . . O _n of the first counter 3 are connected to the input terminals D ₁ , D ₂ . Connected to D _n . Among the wheel speed pulses, a latch wheel speed pulse RI as shown in FIG. 2D is supplied to the L terminal. That is, when this pulse RI is received, the output of the first counter 3 is latched. The output terminals Q ₁ , Q ₂ ...Q _n of the latch circuit 4 are the second
Preset input terminals P ₁ , P ₂ ...P _n of the divider 5 of
connected to. A wheel speed pulse R for presetting is supplied to the PE terminal, and the output of the latch circuit 4 is preset to the second divider 5 at this timing. The above-mentioned high frequency pulse fo is supplied to the CLK terminal, and one pulse is generated from the terminal Q each time the count value of this pulse becomes equal to the preset value. That is, the second divider 5 generates a pulse train having a frequency obtained by dividing the frequency o of the pulse fo by the preset digital value. The pulse train from the second divider 5 is supplied to the CLK terminal of a second n-bit counter 6. R
A preset wheel speed pulse R is supplied to the terminal. This pulse R clears the count value of the second counter 6. This output terminal O ₁ ,
O ₂ ...O _o are connected to input terminals D ₁ , D ₂ ...D _o of a D-latch type latch circuit 7. This latch circuit 7 corresponds to the second counter 6 and has n bits. The latch wheel speed pulse RI is supplied to the L terminal of the latch circuit 7. That is, when this pulse RI is received, the output of the second counter 6 is latched. Output terminals Q ₁ , Q _{2 .} . . Q _o of the latch circuit 7 are connected to the microcomputer 1 described above. Next, the generation circuit of wheel speed pulses R and RI will be explained. This generation circuit includes a wheel speed sensor 8, a waveform shaping circuit 9, and a D flip-flop 10,1.
1 and 14 and NAND elements 12 and 13. The wheel speed sensor 8 is attached to a wheel of a car and generates a signal in the form of a sine wave with a frequency proportional to the rotational speed of the wheel. This signal is the waveform shaping circuit 9
The waveform is shaped here as shown in Fig. 2B.
A rectangular wave fi as shown in is obtained from the waveform shaping circuit 9. This square wave fi is a D flip-flop 10
is supplied to the D terminal of On the other hand, the above-mentioned high frequency pulse fo is supplied to the C terminal, and this pulse fo
As shown in FIG. 2A, the Q output of the flip-flop ₁₀ becomes "1" with the rise of pulse a1, and becomes "O" with the rise of pulse _a4 .
becomes. In other words, as shown in Figure 2C, a pulse whose rising and falling edges are synchronized with the pulse fo.
fi is obtained from the Q terminal of flip-flop 10. In this way, the pulse fi obtained by synchronizing the pulse fi with the clock pulse fo is supplied to the D terminal of the next D flip-flop 11, and is also supplied to one input terminal of the NAND element 12. be done. This flip-flop 11 is also supplied with the clock pulse fo, and the flip-flop 10 in the previous stage receives pulse a ₁ of the clock pulse fo.
A pulse fi' is obtained from the Q terminal triggered by the rising edge of the pulse fi', but since the rising edge of the pulse fi' lags behind the rising edge of the pulse _a1 by about nanoseconds, the flip-flop 11 The rising edge of pulse fi' is not read by the rising edge of pulse ₁ , but is read by the rising edge of the next pulse _a2 . Therefore, the output of flip-flop 11 is "1" at the rising edge of clock pulse _a1 .
and becomes "O" at the rising edge of the next clock pulse _a2 . Flip-flop 1 like this
1 is supplied to the other input terminal of NAND element 12, so at the rising edge of clock pulse _a1 , the output of NAND element 12 becomes "0".
and becomes "1" at the rising edge of clock pulse _a2 . That is, the pulse shown in FIG.
A pulse obtained by inverting RI is obtained from the NAND element 12. The output of this NAND element 12 is the other one.
A power supply is supplied to one input terminal of the NAND element 13, and a power supply as shown in FIG. 2F is supplied to the other input terminal.
At the time of ON, a negative direction pulse is instantaneously generated, and from then on, a “1” signal is supplied, so in the end,
From the NAND element 13, an output obtained by inverting the output of the NAND element 12, that is, a wheel speed pulse RI shown in FIG. 2D is obtained. As mentioned above, this pulse RI is used as a latch pulse for the L of the latch circuits 4 and 7.
Supplied to the terminal. The output of the NAND element 13, ie, the pulse RI, is supplied to the D terminal of the third D flip-flop 14. On the other hand, high frequency pulse fo is supplied to the C terminal. As mentioned above, the output of the flip-flop 11 becomes "0" due to the rise of pulse a ₂ during this pulse fo, but since it becomes "0" with a delay of about nanoseconds, the output of pulse a ₂ becomes "0". At the rising edge, the output of the NAND element 13 is still "1", so the Q output of the flip-flop 14 becomes "1" with the rising edge of the pulse _a2 , and the Q output of the flip-flop 14 becomes "1" with the rising edge of the next pulse _a3 . The output of the NAND element 13, which becomes "0" after a certain delay, is read, and its Q output becomes "0". In this way, a preset wheel speed pulse R as shown in FIG. 2E is obtained from the Q terminal of flip-flop 14. This pulse R is supplied to the first counter 3, the second divider 5 and the second counter 6 as described above. The wheel speed pulses RI and R are obtained in the above manner, and it is clear that these frequencies are proportional to the rotational speed of the wheels and are equal to each other. The wheel rotation speed calculation circuit according to the embodiment of the present invention is constructed as described above, and its operation will be explained next. Assume that the car is now traveling at a constant speed. That is, it is assumed that the wheel rotation speed is at a constant value V. In this case, each signal in the closed loop constituted by circuits 1 to 7 is in a constant state.
At this time, the digital output generated from the microcomputer 1 as a wheel rotation speed calculator is N
shall be. The value of N is proportional to the wheel rotation speed V, and this proportionality constant is determined depending on the required measurement accuracy. The digital output N of the microcomputer 1 is supplied to a first divider 2, and the first divider 2 generates a pulse train with a frequency of fo/N. This pulse train is supplied to the first counter 3. The first counter 3 is reset by the preset wheel speed pulse R, and continuously counts the pulse train of the first divider 2 within a period until the next wheel speed pulse R. Now, since the wheel rotation speed is a constant value V,
The frequency fi (or fi)' of the pulse R is constant. Therefore, the first counter 3 counts fo/Nfi pulses within each period of the pulse R. On the other hand, as shown in FIG. 2D and E, the latch circuit 4 is supplied with the latch wheel speed pulse RI that was generated earlier by a time corresponding to the period of the clock pulse fo. Digital output fo/Nfi of counter 3 is latched.
In addition, since this latch circuit 4 is a D latch type,
When the pulse RI is supplied, the current digital output of the first counter 3 is latched instead of the previous latched contents. The contents of the latch circuit 4 are preset in the second divider 5 by the reset wheel speed pulse R which is generated one cycle later than the clock pulse fo. The second divider 5 generates one pulse each time the count value of the clock pulse fo becomes equal to the set value fo/Nfi. That is, the pulse train of frequency Nfi is transmitted to the second divider 5.
, which is fed to the second counter 6. The second counter 6 is cleared each time a wheel speed pulse R occurs and counts the pulse train from the second divider 5 continuously within each period of the pulse R. Now, since the frequency of the pulse R is fi, the count value for each period is N. This digital output is latched into the latch circuit 7 together with the latch wheel speed pulse RI. Since this latch circuit 7 is also of the D latch type, the digital value of the previous cycle is replaced with a new digital value along with the latch signal (in the steady state, the contents of the latch circuit 7 remain unchanged). The output of the latch circuit 7 is sent to the microcomputer 1.
It is compared with the output of the latch circuit 7, that is, the output of the microcomputer 1, for the previous cycle stored here, and it is determined that they are the same, so that the wheel rotation speed is not corrected and is a constant digital value. N is supplied to the first divider 2. Next, a case will be described in which the brake is applied to reduce the wheel rotation speed in the constant speed state as described above. As the wheel rotation speed decreases, the wheel speed pulse R,
The frequency of RI decreases and its period increases inversely. In other words, assume that the frequency which was fi in the above-mentioned steady state drops by Δfi in the R or RI pulse cycle immediately after applying the brake or several cycles after applying the brake. Then, the second
The count value of counter 6 is from N to Nfi/fi-△
increases to fi. This digital value Nfi/fi-Δfi is latched in the latch circuit 7 by the next latching wheel speed pulse RI, and the contents of this latch circuit 7 are supplied to the microcomputer 1. In the computer 1, it is compared with the digital value N counted within the previous R or RI period, that is, the wheel rotation speed.

[Formula], and △fi is sufficiently smaller than fi, so

[Formula]. However, since N = fi, the change in digital value at this time △
N〓△fi. Therefore, N(1+△fi/fi)=N+
△N. This ΔN is, of course, a digital value, and varies depending on the sensitivity of the wheel speed sensor 8 and how the brakes are applied, but is, for example, 1 in normal anti-skid control. Therefore, if it is set to 1, (N+1)-N-1 is calculated in the computer 1, and this result is subtracted from the wheel rotation speed N in the computer 1 at this time, resulting in a digital value of N-1=N'. is supplied to the first divider 2. From the first divider 2, a pulse train with a frequency of fo/N' is supplied to the first counter 3, and from this counter 3, a pulse train of fo/N'(fi-
A digital value of △fi) is counted and latched in the latch circuit 4 with the next wheel speed pulse RI, and thereby set in the second divider 5 with the reset pulse R delayed by one clock of the high frequency pulse fo. Ru. From this divider 5, a pulse train having a frequency of N'(fi-Δfi) is supplied to a second counter 6. This counter 6 is cleared together with the pulse R that presets the second divider 5, continuously counts the pulse train of the second divider 5 within the next R or RI period, and transfers this count value to the next one. latch pulse RI
However, if the wheel rotation speed in this period, that is, the wheel speed pulse R
Or, unless the frequency of RI is decreased by an amount corresponding to a digital value of 1 from the frequency of R or RI in the immediately preceding period, the digital output of the latch circuit 7 remains unchanged at N'. In other words, if the frequency of RI or R changes further by △f' from the immediately preceding period, then N'-
If N'(fi-.DELTA.fi)/fi-.DELTA.fi-.DELTA.fi'<1, the output of the latch circuit 7 remains N'. Therefore, in this case, the output of the wheel rotation speed calculation section in the computer 1
Since it is equal to N', the wheel rotation speed is not corrected and the computer 1 continues to output the digital value N'. Then, within the next or several periods later period of RI or R, the frequency of the wheel speed pulse RI or R becomes (N
When the frequency of the wheel speed pulse RI or R within the period of RI or R that counted +1) has decreased by more than a value corresponding to a digital value 1, the wheel rotation speed calculator in the computer 1 is activated as described above. 1 is subtracted from the contents of . As described above, according to the circuit of this embodiment, the wheel rotation speed is calculated almost instantaneously, and not only can the measurement accuracy be increased compared to the conventional method, but also the wheel rotation speed per bit can be calculated almost instantaneously. Since the value is constant regardless of whether the wheel rotational speed is high or low, the wheel deceleration can be easily determined. For example, by counting the number of correction bits per unit time for the wheel rotational speed calculating section in the computer 1, the deceleration can be immediately determined. Note that although the case where the brakes are applied has been described above, it is clear that the same effect can be obtained when the vehicle is accelerated. That is, the above −
The same explanation can be obtained by replacing △fi with +△fi. The acceleration of the wheels can also be easily determined for the same reason. Although not shown, the digital output of the wheel speed calculation section of the computer 1 is supplied to the approximate vehicle speed calculation circuit and the slip ratio calculation circuit, and is used as a control signal for the valves that control the brake fluid pressure of the wheels as well as the acceleration and deceleration mentioned above. is formed, but since various configurations are known, a description thereof will be omitted. Although the embodiment of the present invention is configured as described above,
Of course, the present invention is not limited to this, and various modifications can be made based on the technical idea of the present invention. For example, in the above embodiments, the case where the present invention is applied to an automobile has been described, but of course it is also applicable to other vehicles such as two-wheeled motor vehicles. In addition, in the above embodiment, the wheel speed pulses R, RI
A clear signal or a latch signal is provided to the counter or latch circuit each time the wheel speed pulse R,
A clear signal or a latch signal may be obtained every plural cycles of RI, for example every four cycles.
In this way, a plurality of wheel speeds can be calculated using the single circuit shown in FIG. The wheel speed calculation circuit of the present invention has the above-described configuration, and has the extremely remarkable effect of being able to instantaneously calculate the wheel speed and performing the differential operation extremely easily.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a wheel speed calculation circuit according to an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the circuit. In the figure, 1... microcomputer, 2... first divider, 3... first counter, 4, 7... latch circuit, 5... second divider, 6... Second counter, 8... wheel speed sensor, 10, 11, 14... flip-flop.

Claims (1)

[Claims] 1. A wheel speed signal generator that generates a wheel speed signal with a frequency proportional to the wheel rotation speed, and a digital value corresponding to the wheel rotation speed is calculated and output based on the wheel speed signal of this wheel speed signal generator. an arithmetic unit; a first divider that receives the output of the arithmetic unit, counts a constant high-frequency signal, and generates one pulse each time the counted value becomes equal to the output of the arithmetic unit; a first counter that continuously counts the pulses generated by the first divider within the cycle of the wheel speed signal or a period related to the cycle; a second divider that counts high frequency signals and generates one pulse each time the counted value becomes equal to the output of the first counter; and a pulse generated by the second divider. and a second counter that continuously counts within the period or period of the wheel speed signal, and supplies the output of the second counter to the arithmetic unit as a signal based on the wheel speed signal. , the output of the arithmetic unit for the previous cycle or period stored here is compared with the output of the arithmetic unit, and if different, the output of the arithmetic unit is corrected by this difference. Speed calculation circuit.