JPS6153732B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display device, such as a CRT display device, that detects an error position in display data and displays the position.

CRT used as a terminal device for electronic computers
The terminal control device performs data input processing and displays the input data, and if there is a data error, the error position is displayed so that the error can be corrected. That is, when the CRT terminal control device performs data entry and sends it to the central processing unit (CPU), a response signal in response to acceptance of input data is sent from the CPU to the CRT terminal control device. In this case, if there is an error in the entry data, a response signal indicating the error will be sent to
Error information is sent from the CPU. According to this error information, the CRT terminal control device displays an error by, for example, blinking the error character.
Requests the operator to correct the error character. The operator inputs correction data for the error location and retransmits the entry data only for the corrected data field to the CPU. To correct the above error field, move the cursor to the error location and re-enter the correct data. When there are multiple error fields, it is necessary to move the cursor to each error field in sequence. Conventionally, this cursor movement is done manually by an operator, which is very time-consuming. It was troublesome. That is, in the past, there were four operation buttons that moved the cursor in the up, down, left, and right directions, and by operating each cursor movement button, the cursor was moved to the first correction position, and after the error was corrected, the cursor was moved again. The cursor is moved to the next correction position by operating a button, which is very cumbersome.

The present invention has been made in view of the above points, and
It is an object of the present invention to provide a display device that can automatically move and display a cursor to a position corresponding to an error position according to error information from a CPU.

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of the CRT terminal control device will be explained with reference to FIG. In Figure 1, DB is
A data bus that transmits data from a CPU (not shown). This data bus DB is connected to internal bus 2 via interface 1 that operates according to operation commands from the CPU.
A CRT controller 3 and screen memory 4 are connected. Furthermore, a line data memory 5 is connected to the internal bus 2 via a gate circuit _G1 , and a line control memory ₆ is also connected via a gate circuit G2. And above
The CRT controller 3 is given a read/write command R/W1 and an enable signal _E1 from the CPU, and address data is also input via the address bus AB. The CRT controller 3 mentioned above performs reading and writing control of the screen memory 4, cursor movement control, etc., which will be described in detail later.
Read/write command R/W to screen memory 4
2. Give the gate signal GS to the gate circuit _G3 , and give the cursor address data and address register designation signal AS to the address register 7. The data set in the address register 7 is sent to the gate circuit G ₃
is input to. Furthermore, the count contents of the address counter 10 are input to the gate circuit _G3 . The address counter 10 is counted up by a pulse given from the synchronization control circuit 9 for each character scan.

The gate circuit G ₃ selects an input based on the select signal GS from the CRT controller 3 and supplies it to the screen memory 4 . This screen memory 4 consists of a screen data memory SDM and a screen control memory SCM, as shown in FIG. , 4...2n are the areas of the screen control memory SCM. This screen control memory SCM stores, for example, control data indicating error e, dub kit d, and protect p, and control data for controlling display states of reverse r, blink b, and half bright. Therefore, the screen data memory SDM in screen memory 4
The display data stored in the screen control memory SCM is sent to the line data memory 5 via the gate circuit _G1 as described above, and the control data stored in the screen control memory SCM is sent to the line control memory ₆ via the gate circuit G2. sent to.
The line data memory 5 and the line control memory 6 are composed of shift registers, and are circulated once through gate circuits G ₁ and G ₂ for each raster scan of the screen to store and hold data. The line data memory 5 and line control memory 6 store one line of the screen (one line of characters).
Gate circuit from screen memory 4 for each scan
The next line outer material data and control data read out via G ₁ and G ₂ are stored. In this case, the synchronization control circuit 9 controls the gate circuits G ₁ and G ₂
control is performed. The line data stored in the line data memory 5 is sent to the character generator 11. This character generator 11 operates in synchronization with a signal from the synchronous control circuit 9, and generates character data for input line data. This character data is transmitted to the P-S (parallel-serial) conversion circuit 12.
The data is converted into serial data via the converter and sent to the synthesis circuit 13. Further, the control data stored in the line control memory 6 is stored in the detection circuit 14.
A control signal based on the detected content is sent to the synthesis circuit 13 and synthesized with the display data. The signal synthesized by the synthesis circuit 13 is sent as a video signal to a CRT display section (not shown) via an OR circuit 15. Furthermore, this CRT
The output of a coincidence detection circuit 16 that detects coincidence of contents between the address register 7 and the address counter 10 in accordance with a signal from the synchronization control circuit 9 is inputted to the display section via an OR circuit 15. This matching circuit 1
6, the position of the cursor display is detected.
Furthermore, the horizontal synchronization signal H.SYNC is displayed on the CRT display.
and a vertical synchronization signal V.SYNC.

Next, details of the CRT controller 3 will be explained with reference to FIG. CPU to data bus DB
The data applied to the internal bus 2 via the interface 1 is input to an input register 21 or a cursor counter 22 in the CRT controller 3. Further, the read/write command R/W1, enable signal E ₁ , and address data sent from the CPU to the CRT controller 3 are input to the address decoder 23 . Address decoder 23
selects the input register 21 or the cursor counter 22 according to address data from the CPU and issues a write command. The data set in the input register 21 is sent to the control circuit 24 and also sent to the error bit detection circuit 25 via the gate circuit _G4 . Furthermore, the set contents of the input register 21 are returned to the internal bus 2 via the gate circuit _G5 and transferred to the screen memory 4. The control circuit 24 generates the read and write commands R/W2 and gate signals according to the input data.
GS, address register designation signal AS, and other control signals from output lines a to d. That is, the output line a of the control circuit 24
From is a gate signal for gate circuit _G5 , from output line b is an error bit check command, from output line c is a command signal when the correction key ED is operated, from output line d is a cursor when data is input. A movement command is output. The signal output from the output line b of the control circuit 24 is input to the gate circuit _G4 as a gate signal and also input to the AND circuit 26, and the signal output from the output line c is input to the set terminal S of the flip-flop 27. is input. This flipflop 2
The output of 7 is input to the AND circuit 26 and is also sent to the end detection circuit 28 as an operation command. This end detection circuit 28 outputs a detection signal when the count content of the cursor counter 22 reaches the final address position on the screen, and the output signal is sent to the flip-flop 27 via the OR circuit 29 together with the output of the error bit detection circuit 25. It is input to the reset terminal R of. And the AND circuit 26
The output of is sent to the one-shot circuit 31 via the OR circuit 30, and is also sent to the one-shot circuit 31 via the delay circuit 32 and the OR circuit 30.
The output of this one-shot circuit 31 is the control circuit 2
The signal is input to the +1 circuit 34 via the OR circuit 33 along with the signal output from the output line d of No. 4. This +1 circuit 34 increments the contents of the cursor counter 22 by 1 every time a signal is applied from the OR circuit 33. In this case, since the screen data memory SDM in the screen memory 4 is configured with odd addresses, when one pulse signal is output from the AND circuit 26, this pulse signal is transmitted directly and through the delay circuit 32. The pulse signal is input to the one-shot circuit 31, and the one-shot circuit 31 outputs two pulse signals, so that the cursor counter 22 is incremented by two. Further, when display data is input by key operation, a +2 signal is output from the output line d of the control circuit 24 to increment the cursor counter 22 by +2.

Next, the operation of the present invention configured as described above will be explained. For example, when inputting sales data for inventory management, etc., the data is input from the key input section according to a predetermined data format that has been selected and designated in advance and displayed on the CRT display section, as shown in FIG. Data input from this key input section is written to the screen data memory SDM in the screen memory 4. In this case, the screen control memory SCM is provided with a protect bit area P and an error bit area e corresponding to the data stored in the screen data memory SDM to form a format, as shown in FIG. For example, a protect bit "1" is written in the protect bit area P for characters that should not be erased, such as "Hizuke", "Denpiyo No.", and "Tokisaki Code", and character spacing parts. Furthermore, when error information is sent from the CPU to the error bit area e, an error bit "1" is written at the beginning position of the error field. After completing the data input process according to the data format, the user operates the entry key ENT to transfer the input data stored in the screen data memory SCM to the CPU. When transferring this input data, an operation command is given from the CPU to the interface 1 by operating the entry key ENT, and a signal designating the input register 21 is given from the address bus AB. Therefore, a data transfer command by operating the entry key ENT is sent to the input register 2 via the data bus DB.
1. The control circuit 24 decodes that the command input to the input register 21 is a data transfer command, and applies a signal AS to the address register 7 and a signal GS to the gate circuit _G3 . Therefore, the value of the cursor counter 22 is transferred to the address register 7, and this becomes the address of the screen memory 4. Since the cursor counter 22 is initially set to "0" and the screen memory 4 is designated for reading by the R/W2 signal, the contents of the screen data memory SDM are read to the internal bus 2 and the interface 1 and is transferred to the CPU via the data bus DB. The CPU detects errors by checking the screen data sent via the data bus DB to see if each field is in an impossible state, for example, whether the number of digits is within a set range. If an error is detected by this data check, the error information is sent to the screen memory 4 via the data bus DB and interface 1, and an error bit "1" is written in the error bit area e of the screen control memory SCM as shown in FIG. ” to be memorized. In this case, an error bit "1" is stored at the beginning position of the error field. FIG. 5 shows a case where an error occurs in the field for person in charge and unit price. Further, the CPU sends the address data corresponding to the first error bit, that is, the error bit of the person in charge code in the example of FIG. 5, to the CRT controller 3 via the interface 1.
Set in cursor counter 22. in this case,
The CPU sends a write command R/W1 to the CRT controller 3, and also sends address data for specifying the cursor counter 22 to the address bus.
It is sent to the CRT controller 3 via AB.
The CRT controller 3 selects and designates the cursor counter 22 in accordance with a control command from the CPU, and sets the address data corresponding to the first error bit in the cursor counter 22 as described above. Further, the CRT controller 3 outputs an address register designation signal AS from the control circuit 24 to the address register 7, and transfers the contents of the cursor counter 22 to the address register 7. The cursor data held in the address register 10 is sent to a match detection circuit 16 together with the contents of the address counter 10, and a match is detected. The address counter 10 is counted up at regular intervals by a signal from the synchronization control circuit 9, and its contents correspond to the raster scanning position on the screen, that is, the address on the screen. And address counter 1
When the content matches the content of the address register 7 due to the count up of 0, a match detection signal is output from the match detection circuit 16 while the match is maintained, and is sent to the CRT display section via the OR circuit 15. The cursor will be displayed. That is, a cursor is displayed at the beginning of the person-in-charge code, which is the first error field.

In the above state, the operator inputs correction data from the key input section. This corrected data is 1
The flow shown in FIG. 6 is executed every time a character is input. First, data input by key operation is set in the input register 21 in the CRT controller 3, as shown in step A. At this time
A write signal R/W1 and address data specifying the input register 21 are given from the CPU, and data is set in the input register 21. Next, the control circuit 24 outputs the address register designation signal AS, and the contents of the cursor counter 22 are transferred to the address register 7 as shown in step B. The address data set in the address register 7 is transferred to the screen memory 4 via the gate circuit G ₃ under the control of the CRT controller 3.
and specifies the start address of the first error field in the screen data memory SDM.
Also, at this time, a write command R/W2 is sent from the CRT controller 3 to the screen memory 4, and as shown in step C, the correction data held in the input register 21 is sent to the screen data memory SDM via the gate circuit _G5 . written to. Next, the count up signal of the cursor counter 22 is output from the output line d of the control circuit 24, and the contents of the cursor counter 22 are incremented by 2 as shown in step D. This +2 cursor counter 2
The contents of 2 are transferred to the address register 7 as shown in step E, and the next character position in the error field is displayed with a cursor. Similarly, each time one character of correction data is input by key operation, the processing steps A to E are repeated.

After completing the error correction for the first error field, the user first operates the error correction key ED in the key input section in order to correct the next error field. When this error correction key ED is operated, the cursor is shifted to the beginning position of the next error field according to the flow shown in FIG. That is, when the error correction key ED is operated and an error correction command is sent to the control circuit 24 via the input register 21, a "1" signal is output from the output line c of the control circuit 24, and the flip-flop 27 is set. . When this flip-flop 27 is set, its output is sent as an operation command to the end detection circuit 28, and the end detection circuit 28 changes the contents of the cursor counter 22 up to the final address on the screen as shown in step A of FIG. It is detected whether or not it has been reached. If the cursor has not reached the final position on the screen, a "1" signal is output from the output line b of the control circuit 24 and sent to the one shot circuit 31 via the AND circuit 26 and the OR circuit 30. As a result, a one-shot pulse is output from the one-shot circuit 31, and +
1 circuit 34, and the contents of the cursor counter 22 are incremented by 1 as shown in step B. The contents of the cursor counter 22 are immediately transferred to the address register 7, and based on the contents of the address register 7, the contents of the screen control memory SCM in the screen memory 4 are read out to the input register 21 as shown in step C.
The control data read into the input register 21 is sent to the error bit detection circuit 25 via the gate circuit _G4 , and the presence or absence of an error bit is detected as shown in step D. This step D
If no error bit is detected at , flip-flop 27 is held set. Therefore, a one-shot pulse is output from the one-shot circuit 31 using the delayed signal output from the delay circuit 32, and when the cursor counter 22 is incremented by 1 as shown in step E, the process returns to step A. Thereafter, steps A to E are repeated in the same manner, and the cursor is sequentially advanced until an error bit is detected. Then, when the cursor is advanced to the next error field and an error bit is detected in step D, that is, the error bit detection circuit 2
When an error bit detection signal is output from the circuit 5, the flip-flop 27 is reset by this detection signal. Therefore, when a one-shot pulse is output from the one-shot circuit 31 in response to the output of the delay circuit 32 and the cursor counter 22 is incremented by 1 as shown in step F, the cursor shift process ends here. i.e. error correction key
By operating ED, the cursor located at the first error field is automatically shifted to the next error field, and the cursor stops at the beginning position of this error field. In this state, by inputting correction data from the key input section, error correction processing is performed in the same manner as error correction in the first error field. Further, in step A, when the end detection circuit 28 detects that the contents of the cursor counter 22 have reached the final position on the screen, the flip-flop 27 is reset by the detection signal and the cursor shift operation is completed.

As described above, according to the present invention, the cursor can be automatically moved to the error correction position according to error information from the CPU, and error data can be easily corrected.

In the above embodiment, the error bit is provided at a position corresponding to the beginning of the error field, but it may be provided at other positions, for example, corresponding to the entire area of the error field.

Furthermore, if the error field is displayed by blinking or the like, the position of the error field will become clearer.

Further, in the embodiment described above, error bits are stored in the screen control memory, but a memory for storing error bits may be provided independently.

Furthermore, in the embodiment described above, the same number of error bit storage areas as the number of data in the screen data memory are provided, and the positions of error data and error bits are made to correspond to each other, but address values of error data may also be stored. At the time of correction, the above address value is set in the address register.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention, FIG. 1 is a block diagram showing the overall configuration, and FIG.
Fig. 3 is a block diagram showing details of the screen memory in Fig. 1; Fig. 4 is a block diagram showing an example of display data; Fig. 5 is a block diagram showing details of the screen memory in Fig. 1; FIGS. 6 and 7, which show examples of bit and error bit storage, are flowcharts showing the operation contents. 2...Internal bus, 3...CRT controller, 4...
Screen memory, 21... Input register, 22...
Cursor counter, 27...flipflop.

Claims (1)

[Scope of Claims] 1. A first storage means for storing display data; a second storage means for storing error position data indicating a display position of error data among the display data; setting means for reading error position data from the storage means of item 2 and setting a cursor display address corresponding to the error position data; and display means for displaying a cursor based on the set cursor display address. A display device characterized in that the cursor is automatically moved and displayed at a position corresponding to an error position.