JPS6154255B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an ultrahigh-speed logic integrated circuit device.

A conventional method for manufacturing this type of device is as shown in FIG. FIGS. 1a to 1g are cross-sectional views showing a conventional manufacturing method in the order of steps. As shown in Figure 1a, relatively low impurity concentration (10 ¹⁵ cm ^-3 )
On the surface of the semiconductor substrate 1 made of p-type silicon,
The opening 2a is opened so that the selected surface area is exposed.
An insulating film 2, such as an oxide film (SiO ₂ ) having ^a form 3. In addition, the figure b
Region ⁴ in is a ^p
This is the channel cut area. Next, as shown in Figure c, the selected surface area and the insulating film 2 are
When silicon is epitaxially grown over the entire surface of the semiconductor substrate 1 including the semiconductor substrate 1, a single crystal semiconductor region 5a is formed in the selected surface region, and a polycrystalline semiconductor region 5b is formed on the insulating film 2. Then,
As shown in FIG. 4D, after a resist 6 is applied to the surfaces of the single crystal semiconductor region 5a and the polycrystalline semiconductor region 5b, the polycrystalline semiconductor region 5b is partially removed. Next, as shown in FIG. 5E, a p-type impurity such as boron is diffused into one polycrystalline semiconductor region 5b and single-crystalline semiconductor region 5a to form an external base region 7b and an internal base region 7a, respectively. In this case, since the diffusion rate of impurities in the polycrystalline semiconductor region is faster than that in the single-crystalline semiconductor region, as shown in FIG. The single crystal semiconductor region 5a is partially converted into a p-type base region 7a. Note that 8 in the figure e is an oxide film. Next, as shown in FIG. 1f, arsenic (As) is simultaneously diffused into the other polycrystalline semiconductor region 5b and internal base region 7a to form an n ⁺ type polycrystalline collector region 9b and an n ⁺ type emitter region 10, respectively. Form. In addition, 9
a is an n ⁺ collector region diffused into the single crystal semiconductor region 5a. Next, as shown in figure g,
An emitter electrode 11b is provided in the n ⁺ emitter region 10,
A base electrode 11c is provided in the p-type external base region 7b,
In addition, the collector electrode 11a is in the n ⁺ collector region 9b.
form each.

The semiconductor device manufactured in this way has a single crystal region 5a simultaneously formed on the p-type substrate 1 by vapor phase growth.
and polycrystalline region 5b are provided, and both regions 5a and 5b are provided.
In order to provide a collector region, a base region ^, and an emitter region in a single crystal semiconductor region by utilizing the difference in diffusion rate in the By making the collector base junction smaller, the area of the collector-base junction can be reduced, and thus the base-collector capacitance and the collector-substrate capacitance can be reduced. Polycrystalline semiconductor regions 9b and 7, respectively.
Since the thickness of the insulating film is different from the thickness of the insulating film, there is a drawback that wiring defects are likely to occur due to differences in level at the portions 12a and 12c shown in FIG. 1g.

The present invention provides a manufacturing method for reducing the level difference in wiring in this type of ultra-high-speed logic integrated circuit device. FIG. 2 is a sectional view of a main part showing a manufacturing method according to an embodiment of the present invention in order of steps. As shown in FIG. 2a, the surface of a semiconductor substrate made of p-type silicon with a relatively low impurity concentration (10 ¹⁴ cm ^-3 ) is oxidized with an opening 2 a so that a selected surface region 1 a is exposed. An insulating film 2 such as a film (SiO ₂ ) is formed, and then as shown in FIG. 2b,
An n-type impurity such as arsenic (As) is diffused through the opening 2a to form an n ⁺ buried region 3. Note that the p ⁺ region 4 in FIG. 2b is the n ⁺ buried region 3 in the surface region of the p-type semiconductor substrate 1.
This is a p ⁺ channel cut area provided in an area other than the above. Next, as shown in FIG. 2c, when n-type silicon is epitaxially grown on the entire surface of the semiconductor substrate 1 including the selected surface region 1a and the insulating film 2, a single layer of n-type silicon is grown on the selected surface region 1a. A crystalline n-type semiconductor region 5a is formed on the insulating film 2, and a polycrystalline semiconductor region 5a and a polycrystalline semiconductor region 5 are formed on the insulating film 2.
When an impurity such as boron is diffused over the entire surface of the semiconductor substrate 1 as shown in FIG. 2c where b is formed,
Since the diffusion coefficient of the polycrystalline semiconductor region 5b is larger than that of the single-crystalline semiconductor region 5a, as shown in FIG. The impurity introduced region 51a is in the polycrystalline semiconductor region 5b.
An impurity introduced region 51b is formed which is thicker than the thickness of the impurity introduced region 51b.

Next, when the impurity introduced regions 51a and 51b thus formed are subjected to, for example, CF ₄ +O ₂ based silicon dry etching, the p-type impurity regions are quickly etched, and the surfaces of the regions 5a and 5b are suddenly etched. The speed will be slower. Furthermore, since the etching rate of polycrystalline regions is faster than that of single-crystalline regions, a polycrystalline region deeply diffused into p-type is etched about three times faster than a single-crystalline region when viewed from the surface. The difference in level between 5a and 5b is significantly smaller than in the conventional method, and the surface of the polycrystalline semiconductor region 5b and the insulating film 2 are
A semiconductor substrate as shown in FIG. 2e, which has a small level difference with respect to the surface of the substrate, is obtained.

Next, as shown in FIG. 2f, after removing unnecessary portions of the polycrystalline semiconductor region 5b, leaving a part of the surface of the single crystal n-type epitaxial region 5a,
When the p-type impurity is diffused continuously with one polycrystalline semiconductor region, the diffusion speeds of both regions 5a and 5b are different, so that the p-type region 7a is in the single-crystal n-type epitaxial region 5a, and the p-type impurity is in the one polycrystalline semiconductor region 5a. A p-type polycrystalline region 7b is formed entirely in the semiconductor region. Note that the reference numeral 8 in FIG. 2f indicates these p-type regions 7.
These are a mask oxide film when forming elements a and 7b and an oxide film formed during heat treatment. Next, as shown in FIG. 2g, using the oxide film 8 as a mask, an n ⁺ type single crystal region 10 is formed in the P type region 7a within the single crystal region.
and an n ⁺ type polycrystalline region 9 in the other polycrystalline region.
Diffusion formation of b. Next, as shown in FIG. 2h, electrodes 11b, 11a, and 11c are provided in the n ⁺ type single crystal region 10, n ⁺ type polycrystalline region 9b, and p type polycrystalline region 7b, respectively.

In this way, the n-type epitaxial region 5a
is an internal collector region, the n ⁺ polycrystalline semiconductor region 9b continuous to this n-type epitaxial region 5a is an external collector region, the p-type single crystal region 7a is an internal base region, and the p-type semiconductor region continuous to this p-type single crystal region 7a is An npn type transistor is formed in which the polycrystalline region 7b is used as an external base region and the n ⁺ single crystalline region 10 is used as an emitter region, and the base electrode 11c and collector electrode 11a extend on the insulating film 2 and are connected to other elements or (none of which are shown).
In this case, the difference in level between the surfaces of the polycrystalline regions 7b and 9b and the surface of the insulating film 2 is as shown in FIG.
As shown in e, the impurity introduced region is formed and the size is reduced by the amount removed.
Even if the wire is extended upward, breakage at the stepped portion can be prevented. Note that such a collector electrode 1
1a, emitter electrode 11b and base electrode 11
This method is effective when performing multilayer wiring in which an insulating film is provided on top of the insulating film and other electrodes are provided on top of the insulating film, since the effect of the step difference becomes particularly large.

Although this invention has been described above with reference to an example in which an impurity doped region is provided in both a single crystal semiconductor region and a polycrystalline semiconductor region, essentially the impurity doped region is provided only in a polycrystalline semiconductor region where an external region is formed. This objective can be achieved by removing this impurity-introduced region.

As explained above, this invention provides an impurity doped region in a polycrystalline semiconductor region formed on an insulating film, removes this impurity doped region, and forms a base region and a collector region in the remaining polycrystalline semiconductor region. Since electrodes are formed and connected to the surfaces of these polycrystalline base regions and collector regions and extend over the insulating film, it is possible to manufacture highly reliable semiconductor devices with extremely few disconnections due to electrode steps. can.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a conventional method for manufacturing a semiconductor device in order of steps, and FIG. 2 is a sectional view showing a method of manufacturing an embodiment of the present invention in order of steps. In the figure, 1 is a semiconductor substrate, 1a is a surface region, 2 is an insulating film, 2a is an opening, 5a is a single crystal semiconductor region, 5b is a polycrystalline semiconductor region, 51a, 51b are impurity introduced regions, 11a, 11b, 11c is an electrode. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A step of providing an insulating film having an opening on the surface of the semiconductor substrate so that a selected surface region of the semiconductor substrate is exposed, and applying the same semiconductor material as the substrate on the surface region and the insulating film. A step of forming a single crystal semiconductor region on the surface region and a polycrystalline semiconductor region on the insulating film by growing the polycrystalline semiconductor region, introducing impurities from at least the surface of the polycrystalline semiconductor region, A method for manufacturing a semiconductor device, comprising: providing an impurity-introduced region thinner than the thickness; removing the impurity-introducing region; and providing an electrode extending onto the polycrystalline semiconductor region and the insulating film after this step. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity-introduced region is also provided in the single crystal semiconductor region.