JPS6155694B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method for driving the memory in a device in which operations are performed sequentially while reading data from the memory. The subroutine function writes data in a specific area of memory to perform the certain operation when a certain operation is performed among various operations, and then writes this data to the execution of the various operations. Memory capacity is utilized by commonly using the memory in the process. FIG. 1 is a diagram showing the configuration of a known memory and addressing circuit having such a subroutine function, and the following operations were performed. As shown in the figure, the known memory addressing circuit is
The configuration includes a data latch circuit 1, a program counter 2, and a memory 3. In the memory and addressing circuit configured as described above, when the program counter 2 specifies an address corresponding to the need to use a subroutine during its operation, the memory 3 generates a call subroutine instruction. . With this command, the contents of the program counter 2 are transferred to the latch circuit 1, and the contents of the program counter 2 are further changed to the start address of the subroutine, and the operations of the subroutine are thereafter executed. When the final address of the subroutine is specified by the program counter 2, the memory 3 generates a return subroutine instruction. By this command, the value obtained by adding 1 to the contents of the data latch circuit 1 is transferred to the program counter 2. After this, the operation continues from the next address where the call subroutine instruction was generated. In memory and address circuits with subroutine functions, the above operations are executed, and subroutines are used in the process of operation, and although they are extremely effective in this respect, they require extremely large additional circuits such as data latch circuits. However, when these are integrated into semiconductors, the area of the semiconductor substrate (chip area) increases, the number of instructions increases, the control method becomes more complex, and the functions themselves become more than necessary. There is a problem.
In other words, since the data latch circuit 1 shown in FIG. 1 controls the program counter 2 and memory 3, the circuit configuration becomes extremely complicated. This does not pose a problem in large-scale systems, but in the case of small system operation, semiconductors are integrated into one chip. This is extremely inconvenient when integrating. Figure 2 shows a memory using a general page specification method.
This is a diagram showing the configuration of an address designation circuit, and as shown in the figure, the configuration includes a program counter 4, a memory 5, and a page designation data latch circuit 6. In addition, the memory 5 is divided into memory areas 51, 52, . has been done. By the way, in the memory and address designation circuit of the page designation method, it is not possible to designate the entire area of the memory 5 only by the program counter 4, and the program counter 4 is designated by the data latch circuit 6 for page designation. single page,
For example, only addresses within memory area 51 can be specified. Therefore, in order to specify addresses in other memory areas 52, . It becomes possible to specify. Note that memory and addressing circuits using such a page specification method do not have subroutine functions themselves, and although it is possible to perform this function by specifying a page, as mentioned above, Since the number of memories in the two is selected equally, it was inevitable that the memory capacity would be wasted. The present invention provides a method that enables memory with subroutine functions and addressing with a much simpler configuration than the memory with subroutine functions and addressing circuit shown in FIG. It is something to do. In the present invention, an area with a smaller number of memories than other areas, that is, a subroutine page, is provided in a memory area, and a driving method for addressing a memory having a subroutine function is realized with a simple configuration. To provide a memory driving method that uses a designation method in an effective and unique manner, has a subroutine function that cannot be achieved with a conventional page designation method, has a simple configuration, and is excellent in semiconductor integrated circuits. FIG. 3 is a diagram showing the configuration of a memory and an addressing circuit that enable the driving method in addressing of the present invention, including a program counter 7, a memory 8, and a page designating data latch circuit 9.
It also includes a carry stop circuit 10 for stopping the carry of the upper digits of the program counter 7 when a subroutine page in the memory is specified. Note that 81, 82... are memory areas designated by the page designating data latch circuit 9; for example, the memory area 82
Assuming that is a subroutine page, the number of memories in this memory area 82 is selected to be smaller than the number of memories in other memory areas such as the memory area 81. In the memory and addressing circuit having the above configuration, for example, the program counter 7 is
The data latch circuit 9 for page designation has contents of 0 and 1, and this contents are stored in the memory area 81 and the memory area 8.
In addition, the numbers of memory addresses in the memory areas 81 and 82 correspond to 2 to the 4th power (2 ⁴ ) and 2 to the 2nd power (2 ² ), that is, 16 and 4, respectively. Furthermore, when the memory area 82, which is a subroutine page, is specified, the carry stop circuit 10 causes the program counter 7 to change its upper digits, that is, the contents of the upper two bits, from the carry from the lower two bits. The contents of the lower two bits of the program counter 7 are not affected by the carry stop circuit 10, and the contents of the lower two bits of the program counter 7 are not affected by the carry stop circuit 10, and all addresses ( Memory, address designation, and subroutine functions when designation of 4 addresses) is possible will be explained with reference to the following table. Although only page change commands related to subroutine functions are listed in the table, it is assumed that other commands unrelated to subroutine functions are written at addresses where no commands are written.

[Table] In the case of this table, when the values of the program counter 7 are 0, 4, 8, and C, the address of the memory area 82 specified is 10;
11 is designated for 9 and D, 12 is designated for 2, 6, A, and E, and 13 is designated for 3, 7, B, and F, respectively. On the other hand, when the memory area 81 is specified by the page specification latch circuit 9, addresses 00 to 0F are sequentially specified for the values 0 to F of the program counter. By the way, the table shows two types of page change commands, "Page=1" and "Page=0", but the "Page=1" command is such that the address specified by the program counter 7 is When changing from the address written in to the next address, the content of the page designation latch circuit 9 changes from 0 to 1, while the "page = 0" instruction changes the content of the page designation latch circuit 9 from 0 to 1. This is an instruction to change from 1 to 0. Assuming that the operation with the contents shown in the table starts from address 00, the memory addresses that are sequentially specified at this time are as follows. First, addresses 00, 01, and 02 are sequentially designated, and if there is no "page=0" command at address 02, the next address is address 03. However, since the instruction “Page=1” is written at address 02,
Address 03 is not specified, address 13 is specified, and after this, the address changes to address 10, 11, and 12. The next address becomes address 03 due to the "page=0" command at address 12. Note that when the address changes from address 13 to address 10, a carry signal is generated from the second bit to the third bit from the lowest digit of the program counter, but when a subroutine page is specified, the above-mentioned carry signal is generated. As shown, the effect on the third bit is eliminated by the function of the carry stop circuit 10. If this carry stop circuit 10 is not present,
After address 12, address 7 is designated. That is, the carry stop circuit 10 plays an important role in realizing subroutine functional operations. Addresses below address 03 are specified as address 04, address 05, address 06, address 07, address 08, address 09, address 0A, and then address 0A becomes address 13 of the subroutine page by the "page = 1" command. After this, the address changes to address 10, 11, and 12, and the next address becomes address 0B due to the "page = 0" command at address 12.
Furthermore, addresses are designated as 0C address, 0D address, 0E address, and 0F address. While addressing is done in this order, addresses 13 to 12 are used in two different locations in a subroutine manner. As is clear from what has been explained above,
The memory driving method of the present invention can realize a subroutine function using a simple memory and address designation circuit, and also has the effect of not wasting memory capacity because the subroutine page does not have unnecessary addresses.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the configuration of a known memory with a subroutine function and an addressing circuit, Fig. 2 is a diagram showing a page specification type memory and an addressing circuit, and Fig. 3 is a diagram showing a memory driving method of the present invention. FIG. 2 is a diagram showing the configuration of a memory and an addressing circuit. 7...Program counter, 8...Memory, 9
. . . Data latch circuit for page designation, 10 . . . Carry stop circuit, 81, 82 . . . Memory area.

Claims (1)

[Claims] 1 Divide the memory into at least two pages, make one divided page a subroutine page with less memory than the other pages, and provide a page designation data latch circuit, a program counter, and a page designation data latch circuit to designate the page. A carry stop circuit is provided which stops the carry of higher order digits exceeding the memory number of the subroutine page of the program counter when the subroutine page is specified, and the carry stop circuit stops the carry of the upper digits exceeding the memory number of the subroutine page of the program counter, and the carry stop circuit stops the carry of the upper digits exceeding the memory number of the subroutine page of the program counter. A method for driving a memory, characterized in that addressing within a page is specified by the program counter.