JPS6155808B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to relaxation oscillators, and more particularly to relaxation oscillators that use a field effect transistor (hereinafter FET) gate circuit to sense the charge level of a timing capacitor.

The relaxation oscillator generates a sawtooth wave with a period determined by the time required to charge the capacitor during each cycle of oscillation. In a conventional relaxation oscillator, the voltage across a timing capacitor is applied to the gate circuit of a common drain amplifier FET, causing the drain-source channel of that FET to conduct when the capacitor's charge level exceeds a certain threshold voltage. By this, the charge level of the capacitor was detected, and the conduction of this FET activated the switch for discharging the capacitor, but this method tends to have the following drawbacks. That is,
The amplitude of the sawtooth wave can be constrained to a value that is directly dependent on the FET's threshold voltage, reducing it below the required operating voltage of the oscillator; tends to depend on the threshold voltage of the FET, which undergoes changes in

A relaxation oscillator embodying the invention eliminates the above disadvantageous tendency by connecting the gate circuit of the FET in series with the timing capacitor between the operating voltage supply terminals. A FET for sensing the level of charge applied to the timing capacitor maintains its channel conductive while the timing capacitor is charged to a level close to its operating potential;
Since its gate circuit does not have a clamping effect, it is of a conductive type that allows conduction of the channel without charging the timing capacitor. The charge level on the capacitor is then sensed indirectly by measuring the difference between that voltage and the operating voltage instead of directly measuring the voltage across it. The available operating voltages under most operating conditions greatly exceed the FET's threshold voltage, especially when choosing the threshold voltage so that the FET can operate at very low current levels with weak channel reversals.
Under these operating conditions, the capacitor is charged to a voltage very close to the operating voltage, so that the amplitude of the sawtooth voltage across the timing capacitor depends primarily on the operating voltage rather than the threshold voltage of the FET. Therefore, the frequency of oscillation is also
It becomes less dependent on fluctuations in the threshold voltage of the FET.

Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings.

In the oscillator 10 of FIG. 1, a current source I ₁ is connected to charge a capacitor C ₁ from a voltage source +V, and switch means 12 are provided for discharging the capacitor C ₁ . The switch means 12 becomes conductive when a closing signal is applied to its terminal _T1 , and exhibits hysteresis characteristics between its conductive state and its disconnected state. generating a closing signal for the switching means whenever C ₁ reaches a predetermined charge level without substantially affecting the charging rate of capacitor C ₁ and drawing substantially no power during charging of that capacitor; A threshold device 14 is provided to stop the signal when C ₁ is discharged below its predetermined charge level.

As is common in many relaxation type oscillators,
The charge level of C ₁ controls the output signal of the oscillator 10, which charge level is divided into a low value when the switch means 12 changes from closed to open circuit and a high value when the switch means 12 changes from open to closed circuit. The oscillation frequency changes continuously between The high output value of the oscillator 10 is equal to the predetermined charge level of C ₁ since the threshold means 14 provides a switch means closing signal whenever C ₁ reaches the predetermined charge level. C ₁
A resistor may be connected in series with the switch means 12 to adjust the discharge rate and oscillation frequency of the switch.
C ₁ rapidly discharges below a predetermined charge level,
The closing signal from the threshold means 14 is only applied for a very short time. The hysteresis characteristics of the switch means 12 then determine when to transition from a closed to an open state to prepare the oscillator for the next cycle of operation. Although many embodiments of the invention are possible for switch means 12 and threshold means 14, the circuitry of a preferred embodiment of both is shown in FIG. As switching means 12 a silicon controlled rectifier (hereinafter referred to as SCR) 16 is used, the anode of which is applied the charge level of C ₁ , the cathode connected to the reference level (earth) of C ₁ and the gate T ₁ A closing signal is applied. +V in the threshold value means 14
Common source connected MOS between power supply and ground point
The series circuit between the source-drain channel of the transistor Q ₁ and the constant current generator I ₂ which is located in the drain circuit of the transistor Q ₁ and forms a current discharger is below the threshold of the current flowing in the channel of the transistor Q ₁ . The circuit means 18 are inserted with circuit means 18 for applying a switch means closing signal in response to a decrease in . A conventional CMOS inverter circuit in this circuit means includes a pair of complementary MOS transistors Q ₂ and Q ₃ . The gates of transistors Q ₂ and Q ₃ are both connected between the drain-source channel of Q ₁ and I ₂ , and the drain-source channels of Q ₂ and Q ₃ are connected in series between +V and ground. It is connected. The gate of Q ₁ is connected to the charge level of C ₁ ,
The inverter output from the connection point of the drain-source channels of Q ₂ and Q ₃ is connected to T ₁ of the switch means 12.
is connected to give a closed circuit signal to this.

As soon as SCR 16 becomes non-conducting (switch means 12 becomes open circuit), the current from _I1 is
As C ₁ begins to charge towards the +V level, the drain-source channel of Q ₁ conducts due to the negative gate-source voltage, and the gates of Q ₂ and Q ₃ receive +V.
is applied virtually as is. As a result, the drain-source channel of Q ₃ becomes conductive due to its positive gate-source voltage, providing ground potential as the output of this CMOS inverter and keeping the SCR 16 from conducting.
As the charge level of C ₁ increases, the negative gate-source voltage applied to Q ₁ decreases, and the drain-source channel current of Q ₁ decreases, causing Q ₂ ,
The gate-source voltage of Q ₃ decreases. then Q ₂
the drain-source channel of becomes conductive due to its negative gate-source voltage,
+V is supplied as the output of the CMOS inverter.
SCR16 is made conductive and _C1 is discharged. The negative gate voltage applied to Q ₁ as C ₁ discharges.
The source-to-source voltage increases and the drain-source voltage of _Q1 increases.
The channel becomes conductive, stopping the closing signal applied to the gate of SCR 16. but,
The SCR 16 remains conductive until the holding current required to maintain its conductivity cannot be secured due to the discharge of _C1 .

After that, the conduction state of this SCR 16 is changed to the oscillator 10.
continues to change at a frequency twice the frequency of . This frequency is determined by the gate-source voltage required to reduce the channel current of Q ₁ and the holding current required to maintain conduction of the SCR 16.
The latter, i.e. by means of the holding current, the switching means 12
The hysteresis characteristics of are also determined. The charging speed of C ₁ is
It is not affected by Q ₁ because the gate of Q ₁ only applies a capacitive load and draws almost no current. Moreover, since substantially ground potential is applied to the output of the threshold means 14 during the charging of C ₁ for a large part of each frequency cycle, the threshold means 14 dissipates substantially no power during this period. . Furthermore, the first
The circuit shown can be easily integrated on just one board,
A pair of complementary bipolar transistors are provided as the SCR 16, and their emitters are connected separately as an anode and a cathode, respectively, and their collectors are connected to the base of the other.
One of the base connections can be connected as the gate of the SCR.

MOS transistor followed by the drain of Q ₁
Because it is coupled to the extremely high input impedance gates of Q ₂ and Q ₃ , the current that needs to be drawn by the current drainer I ₂ to make Q ₂ conductive and cut off Q ₃ is a weak channel in Q ₁ . It only needs to be small enough to operate within the inversion region. Current discharger I ₂
This current requirement is met by using a standard size MOS transistor as Q ₁ , which _operates to meet the current requirement _of only 100 nA due to It is also possible to reduce the source-to-gate voltage to be applied to Q ₁ in order to condition it to supply, and if Q ₁ is a standard size MOS transistor, the current demand of the current sink I ₂ to be
It is also possible to obtain a temperature-independent source-to-gate voltage in which _Q1 supplies a drain current sufficient to meet the current requirement by increasing the voltage to the 100 μA range. However, raising the demand in this way increases the power consumption in the threshold means 14 and also increases the source-to-gate voltage required for switching.

FIG. 2 shows the circuit of a monostable multivibrator 20 as another switching means 12' for use in another embodiment of the invention. This multi vibrator 2
0 are bipolar transistors of the same conductivity type whose main current paths are connected in parallel between the current source I ₃ and the ground point.
Including Q ₄ and Q ₅ .

A closing signal is applied to the base terminal T′ ₁ of Q ₄ , while the base of Q ₅ is connected to the current source I ₄ through the capacitor C ₂ .
and is grounded via a diode _D1 , which has the opposite polarity to the base-emitter junction of _Q5 . _I4 is grounded through the drain-source channel of a common source-connected MOS transistor _Q6 , and is also connected to the gate of another MOS transistor _Q7 . The gate of Q ₆ is connected to I ₃ and when the switch means ₁₂ ' is substituted for the switch means ₁₂ of FIG. shall be. +V is applied to I ₃ and I ₄ .

When the closing signal is not applied to the multivibrator 20 from the base of Q ₄ , switch means 1
2' remains open, allowing charging of capacitor _C1 in FIG. This is because the drain-source channel of Q ₆ conducts due to its positive gate-source voltage, and as C ₂ discharges and the gate-source potential of Q ₇ becomes negative, its drain-source channel becomes non-conducting. This is because it becomes conductive. When a closing signal is applied from the threshold means 14 to the terminal T ₁ ', the switch means 12' changes to the closed circuit state and C ₁
discharge. This is because Q ₄ conducts and the positive gate-source voltage on Q ₆ disappears, causing Q ₆ to become non-conducting and I ₄ to begin charging C ₂ towards the +V level, causing a positive voltage on Q ₇ . By applying a gate-source voltage, its source-drain channel conducts and discharges _C1 . The displacement current during charging of _C2 creates a positive voltage at the base of _Q5 .
Since Q ₅ is conductive, Q ₆ remains non-conducting even after the closing signal ends and Q ₄ returns to non-conducting. When C ₂ is sufficiently charged and its displacement current disappears, Q ₅ stops conducting, so Q ₆ becomes conductive and Q ₇ becomes non-conductive, starting the charging cycle of C ₁ . During each charging period of C ₁ Q ₆ cooperates with D ₁ to discharge C ₂ . Therefore, if switch means 12' is replaced by switch means 12 of FIG. 1, C ₁ will charge and discharge during each frequency cycle of oscillator 10, the frequency of which is determined by the charging time of C ₂ . The circuit configuration of multivibrator 20 is SCR
16, but exhibits a precise reset function with known hysteresis characteristics. Needless to say, when it is desired to make the frequency of the oscillator 10 variable, a variable capacitor can be used for _C2 .

FIG. 3 shows impulse factor means 22 for producing an output from oscillator 10' for a portion of each frequency cycle thereof. The oscillator 10' uses this shock coefficient means 2
The oscillator 10 of FIG. 1 is essentially the same as the oscillator 10 of FIG. 1 with the exception of the oscillator 10 of FIG. The MOS transistor Q' ₁ and the current drain I' ₂ are connected in series in the threshold means 14' in the same way as described above for the threshold means 14, but the diode D _{2 is}
It is inserted between +V and the drain-source channel of _Q'1 to carry the current required for this. In the duty factor means 22 the diode D ₃ , the drain-source channel of the MOS transistor Q ₈ and the current sink I ₅ are connected in series between +V and ground. This shock coefficient means 22 also includes a pair of complementary type components included in a normal CMOS inverter circuit.
MOS transistors Q ₉ and Q ₁₀ are included.
The gates of Q ₉ and Q ₁₀ are both connected to the connection point between I ₅ and the drain-source channel of Q ₈ ,
The source channel is connected in series between +V and ground. The charging potential of C′ ₁ is Q′ ₁ and
Q applied to each gate of ₈ , this shock coefficient means 2
The output of No. 2 is taken out from the connection point of the drain-source channels of Q ₉ and Q ₁₀ .

Oscillator 10' operates substantially similar to oscillator 10 of FIG. ₁ to create a continuously alternating charge level at C'1. Although Q′ ₁ and Q ₈ and I′ ₂ and I ₅ may have different structures, here, the oscillator 1
In order to facilitate the explanation of the operation of the impact coefficient means 22 within 0', it is assumed that Q' ₁ and Q ₈ and I' ₂ and I ₅ have the same structure. However, for example, by using semiconductor junctions having the same diode characteristic shape but different areas, D ₃ is configured to have a larger forward bias junction voltage than D ₂ . Therefore, whenever the switch means 12'' is opened, C' ₁ starts charging towards +V, and Q' ₁ and
The gate-source voltage of _Q8 is
This is the value that makes the source channel conductive at the same time. Whenever Q ₈ becomes conductive, Q ₁₀ in the inverter becomes conductive and the output terminal of the impulse coefficient means 22 is brought to substantially ground potential. When the charge level of C′ ₁ approaches +V, D ₃ has a higher forward bias voltage than D ₂ , so Q ₈
becomes non-conducting before Q′ ₁ . When Q ₈ becomes non-conductive, Q ₉ of the inverter becomes conductive and the shock coefficient means 22
generates +V at the output terminal of When C' ₁ reaches a predetermined charge level, Q' ₁ of threshold means 14' becomes non-conducting and C' ₁ discharges to generate a negative closing signal for switch means 12'_' . and Q ₈ become conductive again.The output terminal of the duty factor means 22 then returns to ground potential and the next duty cycle begins.Therefore, the duty coefficient means 22 is short and controlled during each cycle of oscillation. It functions to produce a high output level during a certain section where it is easy _to
It can be increased or decreased by increasing or decreasing the forward bias voltage of _D3 .

It will be readily understood by those skilled in the art that if the output of the shock coefficient means does not need to be of a particularly short duration, D ₂ of the threshold device 14' may be unnecessary. We also use complex integrated circuit manufacturing techniques _to
By adjusting the oxide film thickness and doping of Q′ ₁ , D ₂
Or the output of the impact coefficient means can be obtained without _D3 .

The main technical effects of the present invention explained through the above embodiments are summarized as follows. That is, since this invention uses a common source connected FET as the element for sensing the voltage between the terminals of the timing capacitor, (a) the range (amplitude) of the voltage between the terminals of the timing capacitor and the oscillation frequency determined by this range; The range does not depend on the threshold voltage of the FET that senses the charging voltage of this capacitor.
(b) Fluctuations in the threshold voltage of the sensing FET have little effect on the operating characteristics; (c) discharge of the timing capacitor is initiated by a decrease in the drain current of the sensing FET below a certain threshold; Since this threshold value is determined by the constant current source connected to the drain of the FET, the discharge start timing is controlled by selecting this current threshold value, making it easier to perform accurate control than with conventional voltage control methods. be able to. (d) Furthermore, in accordance with the above (c), the oscillation frequency can be accurately controlled. Furthermore, the above sensing FET
The effect of connecting a constant current source to the drain circuit is that (e) this constant current source acts as a load with infinite impedance in the FET drain circuit, allowing the FET to operate at maximum gain; FET in threshold means oscillation frequency
(Q ₂ , Q _3, etc.) and elements in discharge circuits (SCR16, etc.)
It may be possible to become insensitive to threshold fluctuations.

Although the present invention has been disclosed by describing a small number of embodiments, it is understood that various modifications may be made to these embodiments in terms of their configuration and the details of the coupling arrangement of parts within the technical scope of the present invention. As will be obvious to those skilled in the art, the above description should be construed as illustrative rather than limiting.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a relaxation oscillator embodying the invention, with each block showing a preferred embodiment of the invention. FIG. 2 is a schematic diagram of another switching means used in a modification of the oscillator of FIG. FIG. 3 is a schematic block diagram of another embodiment of the invention applying a shock coefficient characteristic during each oscillation period. C ₁ ... timing capacitor, I ₁ ... current source,
I ₂ ... constant current source (current discharger), Q ₁ , Q ₂ , Q ₃ ...
FET, 12... switch means, 14... threshold means, 16... SCR.

Claims (1)

[Claims] 1 Polar charging in which a first plate is connected to a first potential supply terminal and receives a reference potential, and a second plate is connected to a charging circuit to increase the potential of that plate in the direction of the operating voltage. a timing capacitor receiving a current; a gate electrode connected to a second plate of the capacitor; and a source electrode and a drain electrode connected to a second potential supply terminal to which the operating voltage is applied. a common source connected field effect transistor having a conductivity type that conducts during the charging process of the capacitor; and an output connected to the drain electrode to supply a current of a predetermined value substantially independent of its own potential to the drain electrode. the first and second terminals having terminals;
a constant current source coupled to one of the potential supply terminals of the
and a discharge circuit controlled based on the potential of the drain electrode, the discharge circuit being connected in parallel to the capacitor and configured to discharge when the drain current of the transistor falls below a threshold determined by the constant current source. a relaxation oscillator including a switch for discharging the capacitor in response to .