JPS6158237A - Pattern forming method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a pattern forming method used for LSI and the like.

[Technical background of the invention and its problems]

Conventionally, the pattern formation method used for L3I was PEP (PEP), in which the pattern was extracted using a photoresist as a mask.
The photo-Egrave-Process) process was common. On the other hand, methods of forming fine patterns using self-aligned films have recently attracted attention.

For example, as described in JP-A-58-217499, an oxide film (52) is formed on the surface of a silicon substrate (51), and then a polycrystalline silicon layer (53) is formed.
Form a Butter Jung. Then, the entire surface is oxidized to form a thin oxide film (54) (Fig. 5a). Next, the entire surface is subjected to reactive ion etching to selectively form a thermal oxide film (54) on the sidewalls of the polycrystalline silicon film (53). ) are left in a self-aligned manner (Fig. 5b). Then, if desired, a polycrystalline silicon layer (53) is left.
(Fig. 5c).

As a result, a finer pattern than that achieved by the PEP process can be formed. However, in the past, although it was possible to form linear patterns, there was no way to form branched patterns. Therefore, there were restrictions on pattern design.

[Purpose of the invention]

An object of the present invention is to provide a pattern forming method that can increase the degree of freedom in designing a self-aligned film pattern.

[Summary of the invention]

In the present invention, a recess is provided on the main surface of the substrate, and then a self-aligned film is selectively formed on the side wall of the recess, and at this time, the self-aligned film is provided with a branched portion by providing a narrow portion in the recess. It is something.

〔Effect of the invention〕

According to the present invention, a self-aligned film pattern having one branch can be realized, whereas conventionally only a closed loop pattern could be obtained.

Therefore, by using this alone or in combination with a linear or closed loop self-aligned film pattern, the degree of freedom in designing a pattern forming method using a self-aligned film can be greatly improved.

[Embodiments of the invention] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the application to a wiring pattern, with (a) showing a plan view and (b) to (d) showing cross-sectional views of the process. Namely, first.

Form the elements necessary for a P-type silicon substrate (1υ). For example, form MOSFETs and diffusion wiring. (Lz indicates the male diffusion layer obtained in this way. Next, 1μ
A thick silicon oxide film a3 is formed flat.

If the underlying layer is uneven, the silicon oxide film αJ can be formed flat by etchback, bias sputtering, or the like. Next, contact holes CI to C are formed. Each contact hole is enlarged! [, Opened for MOSFET gate electrode, polycrystalline silicon wiring, etc. Next, a conductor film, for example, a male polycrystalline silicon layer α, is evenly embedded in each contact hole (FIG. 1b).

After this, a 2μ thick silicon oxide film a9 is formed on the entire surface,
pattern. As a result, the wide part (5) has 25
μ, a concave portion with a width of 1 μ is formed in the narrow portion (B). Then, a conductive film, for example, W
(tungsten) film αQ is grown.

The thickness of the grown film was 0.5 μm (FIG. 1C). Besides W, Mo
, At, n+ polycrystalline silicon, etc. can also be used. Next, reactive ion etching (RI) using CCt4 gas was performed.
This is etched by 0.5μ in the vertical direction using E).

As a result, a self-aligned film pattern of the W film αe is selectively formed on the sidewall of the silicon oxide film α9 (FIG. 1d). Thereafter, a resist pattern is provided in the area surrounded by the broken line in FIG. 1(a), and the unnecessary W film αQ is removed. After this, the resist butter 7 is removed and the entire surface is covered with an oxide film. The previously formed silicon oxide film α9 may be removed and then covered with an oxide film. Alternatively, a wiring layer can be further formed.

In the above manner, between the contact holes C+ and Cz, C,
, C, and C, -C, are connected. Mo and C5~C
A branch pattern is formed by the W film αQ that connects the 8 spaces.

In this manner, branch wiring can be formed in this embodiment. Therefore, when wiring is formed using the self-aligned film, the degree of freedom in designing the wiring pattern can be improved.

FIG. 2 shows a modification. The manufacturing process is the same as in the above embodiment, so the explanation will be omitted. In this example, between contact holes C9 and CI0, IC11-C1)1, C, .

The cry is connected by a W film αω.

Further, high-speed operation can be realized by branch wiring as described above. For example, when transmitting a signal from bc to c, -1c, lc, l or from C14 to ast C1)+C□, C1, the wiring distance is short, so the wiring resistance is small and the signal is transmitted quickly. Further, if desired, the step of removing the W film αe outside the broken line may be omitted.

FIG. 3 shows an embodiment in which the present invention is applied to an electrode of an E''FROM (al is a plan view, and (b) to (d) are cross-sectional views of the process.

That is, first, a field region of the P-type silicon substrate 1)) is etched to form a trench, and a deposited insulating film is buried flat in the trench to form a field insulating layer 03.

Next, the entire surface of the substrate is oxidized to form a 500^ thick gate oxide film (
form). Then, the gate oxide film on the substrate in the rewriting area (C) is removed, ions are implanted there to form a single layer G4), and a 100A thick tunnel insulating film 09 is formed on its surface by thermal oxidation. . Next, a 1 μm thick phosphorus-doped polycrystalline silicon layer is formed and patterned to form a floating gate FG. During this patterning, the exposed gate oxide M133 and the tunnel insulating film are also removed.

Next, the whole is thermally oxidized again to form a floating gate (
(to) A second gate hardening film 07) having a thickness of 100 OA on the surface and 50 OA on the substrate surface is formed. Due to this.

A concave portion having a width of 8μ in the wide portion (A) and a width of 0.8μ in the narrow portion (B) is formed on the main surface of the substrate. Next, a polycrystalline silicon layer doped with phosphorus was formed to a thickness of 400 OA by the CVD method, and CF4+H! Etching is performed to a thickness of 400 OA in the direction perpendicular to the substrate by RIE using gas. And the exposed second gate oxide film 13? ) to remove. As a result, the first control gate electrode CG1 (to) made of the polycrystalline silicon layer is formed. Then, using this as a mask, ion implantation is performed to form an n source C31 and a drain C4 (FIG. 3b). Thereafter, the surface is made flat with a silicon oxide film (41), and a third gate oxide layer (42) having a thickness of 100 OA is formed on the polycrystalline silicon by thermal oxidation.

Next, a polycrystalline silicon layer doped with phosphorus is formed and patterned to form a second control gate electrode CG, (43
) (Figure 3C). After this, a silicon oxide film (44) is formed on the entire surface, a contact hole reaching the drain OG is opened, and an At wiring (45) is formed (Fig. 3d).
).

Write to all cells ov, CG, 7-space (39)
, C.G.

is +20V, CG, CGz of non-selected cells are set to Ov, and drain QQ is set to 0■ or open. As a result, FG has a high potential, and electrons are injected into FG from n+ff1(2), which has the same potential as the source.

When erasing, select source (to) +20V for all cells and set 7'
S: CGs, CGs 'e OV s Non-R selection cell (7) CG1 and CO2 are set to +20V, and the drain is set to Ov or open. This causes the FG to have a low potential, and electrons are emitted from the FG to the layer.

The cell contents are read by applying a selection potential of +5■ to CG and detecting the cell contents by checking the conduction and non-conduction between the source (to) and drain (40).CG.

Since the O7 set gate is configured as follows, even if the lower FG becomes normally on due to rewriting, selective reading can be performed.

In this example, a chain-like self-aligned electrode is formed, and E'
Higher density and faster rewriting of FROM has been achieved.

Alternatively, the second control gate electrode CGx (43) may be eliminated and the rewrite region (C) may have one layer (B) extending from the drain (41 side).Also, in the above two memory examples, polycrystalline silicon A 70-ring gate (to) is formed in a row in each cell in the lateral direction, and a first control gate electrode (to) is formed on both side walls of the gate by Mo, oil silicide, etc. by etching the entire surface by RIE to form self-alignment. However, it is also conceivable to separate only the floating gates between the valley cells by selective etching, but in this embodiment, the process can be further simplified.

FIG. 4 shows an example in which the method is applied to well formation on an LSI substrate. First, a silicon oxide film mask (47) is formed on the main surface of a P-type silicon substrate (46), and the substrate is etched to a depth of 2μ.As a result, the wide part (A) is etched to a depth of 15μ, and the narrow part (T) is etched to a depth of 1μ. A recess of width is formed. Next, CV
A silicon oxide film (48) with a thickness of 0.5 μm is formed by method D (@4 b). Next, this is etched by 0.5μ by RIE using CI'' gas.Then, seven layers of first-base silicon (49) are epitaxially selectively grown (Figure 4c).
, the mask 1471 is removed (FIG. 4a). Such a substrate has n-We 1) arranged in a dense mosaic, and p-ch
, NchMO8FET can be provided to LSIs that coexist. In addition, in the step of FIG. 4(b), it is also possible to form silicon oxide M (4B) by thermal oxidation using a mask (4?) as a silicon nitride film, and then to form a self-aligned film by RIE. .

Furthermore, the present invention is not limited to the above example, and can be implemented with various modifications. For example, in FIG. 5, two polycrystalline silicon layers are provided close to each other, and with a processing mask, such as a silicon oxide film, left on the surface, W is selectively vaporized on the sidewall of the pattern using WF6+H2 gas. Let it grow, the fifth
In Figure (c), the self-aligned film 64) can be made of such a W film and can also be obtained as a pattern having 98-shaped or chain-like branches. If the silicon oxide film 5z is etched using the mask r54), it can be used as an ion implantation mask.

As described above, according to the present invention, a pattern with branches can be obtained, and by combining this alone or with a linear or closed-loop self-aligned film pattern, there is freedom in designing the pattern formation method of the self-aligned film. It is possible to significantly improve the level.

[Brief explanation of drawings]

FIG. 1(a) is a plan view of an embodiment of the present invention, (b) to (d)
) is a sectional view showing the process, FIG. 2 is a plan view of another embodiment, FIG. 3(a) is a plan view of another embodiment, and (b) to (d)
) is a cross-sectional view showing the process, FIG. 4(a) is a plan view showing still another embodiment, (b) and (c) are cross-sectional views showing the process, and FIGS. ) is a sectional view illustrating a conventional example. In FIG. 1, 1)...Pa silicon substrate, 12...n+ layer, 13
゜15...Silicon oxide film, 14...n polycrystalline silicon layer, 16...W film, A...wide part of recess, B
...Narrow width portions of the recesses sC1 to C8...Contact holes. Agent Patent Attorney Noriyuki Chika (and 1 other person) Figure 1 Figure 2 Figure 3 Figure 3 Figure 4

Claims (2)

[Claims] (1) A step of providing a recess on the surface of the substrate, and a step of selectively forming a self-aligned film on the side wall of the recess, and forming a self-aligned film with a branched shape by providing a narrow portion in the recess. A pattern forming method characterized by: (2) Pattern formation according to claim 1, characterized in that a self-aligned film is provided by growing a film by a vapor phase growth method and then etching the film in a direction perpendicular to the main surface. Method.