JPS6158984B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory with a high degree of integration and a fast read/write speed.

Dynamic RAM (Random RAM) is based on the concept of static induction transistor (hereinafter referred to as SIT).
Regarding Access Memory), please refer to the patent application No. 52-18465.
It was detailed in Japanese Patent Application No. 1983-20653 "Semiconductor Memory Device", Japanese Patent Application No. 35956-1983 "Semiconductor Memory", and Japanese Patent Application No. 36304-1983 "Semiconductor Memory". Furthermore, RAM that can be written with light and that can store images was detailed in Japanese Patent Application No. 52-37905 ``Semiconductor Memory.'' As for non-volatile memory, a part of it is published in Japanese Patent Application No. 18465, ``Semiconductor Memory'', and an improved version of it is published in Japanese Patent Application No. 18465, 18465.
No. 72352 "Semiconductor Memory" and Japanese Patent Application No. 1983-83226 "Semiconductor Memory".

What the memory cell structures of these semiconductor memories have in common is that the degree of integration is increased by configuring the memory cells in a three-dimensional structure, such as by providing cells inside the semiconductor rather than on the semiconductor surface. It is in. This is in contrast to conventional MOSFET memory, which has a structure in which the FET electrodes and capacitors that make up the memory are all placed on the surface. at the same time,
Because it uses bulk conduction rather than surface conduction, one of its features is that carrier mobility is high and writing and reading speeds are fast.

Figure 1 shows a specific example of these semiconductor memories.
1 is a plan view, b is a cross-sectional view taken along the line A-A' in FIG. a, and c is a cross-sectional view taken along the line B-B' in FIG.
Of the two main electrodes 11 and 13 made of n ⁺ regions, 11 is a floating electrode surrounded by a P region 15. Here, 11 is called a source and 13 is called a drain. P region 14 serves as the gate of a static induction transistor (SIT). P region 15 is a substrate, 13' is an electrode metal connected to drain 13 and serves as a bit line, and 14 is a word line connected to gate 14. 15' is a contact electrode of the substrate, 1
6 is an insulating layer such as SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ or a composite insulating layer combining multiple of these;
is these insulating layers or insulating resin such as polyimide. The structure is such that an SIT whose source is a floating electrode is placed at each intersection of a word line and a bit line. The impurity density of each region is 11 = 10 ¹⁷ ~
10 ¹² cm ^-3 , 12 is about 10 ¹⁰ to 10 ¹⁶ cm ^-3 , 13 is about 10 10 to 10 16 cm -3
10 ¹⁸ to 10 ²¹ cm ^-3 , 14 to 10 ¹⁵ to 10 ²¹ cm ^-3 ,
15 is about 10 ¹⁴ to 10 ¹⁸ cm ^-3 . The width of the channel portion surrounded by the gate 14 is determined by the impurity density of the n ^- region 12, and is set so that the channel is completely pinched off and in a cutoff state only by the diffusion potential between the gate and the channel region. . Of course,
Even if charge is accumulated in the source region 11, which is also a storage capacitor, and the potential rises to a certain level, the potential barrier is such that electrons will not flow from the drain 13 toward the source 11 unless a readout voltage is applied from the outside. The dimensions and impurity density must be such that impurities occur in the channel. For example, when the impurity density in the n ^-region is 1×10 ¹³ cm ^-3 , 1×10 ¹⁴ cm ^-3 , and 1×10 ¹⁵ cm ^-3 , the channel widths are 20 μ, 6 μ, and 2 μ, respectively.
Select an appropriate value below μ. This does not apply in the case of an operation in which a reverse voltage is applied to the gate when data is stored in the memory cell, and the gate is set to, for example, an O voltage during reading and writing. For example, the channel may be set to be in a conductive state when the gate is at O voltage, and to be in a sufficiently cut-off state when -3V is applied to the gate. The shorter the distance between the source and the drain, the shorter the travel time of electrons during writing and reading, which is desirable. For example, it is about 0.5 to 15μ.
The equivalent circuit of one memory cell drawn in FIGS. 1a, b, and c can be expressed as shown in FIG. 1f.
18 is a storage capacity. In Figure 1 a, b, c,
The storage capacitor is constituted by the junction capacitance between the region 11 and the substrate 15. When writing data, a predetermined positive voltage is applied to the bit line 13'. At the same time, a positive voltage is applied to the gate (word line) to lower the height of the potential barrier created in the channel, so that electrons flow from the source region 11 to the drain. As the electrons flow out, the source 11 is positively charged and the potential becomes positive and high. When the write voltage and the source potential are balanced, the flow of electrons stops, and when the write voltage is removed, the charged state of the source region 11 changes. is retained as is.

There are two types of write addressing depending on the configuration of the channel section. If the channel width is narrow and the impurity density is set low enough to create a sufficiently high potential barrier in the channel (a), simply applying a positive voltage to the bit line will not
Since the potential barrier cannot be lowered sufficiently, a voltage is applied to the bit line to the gate of the memory cell to be written, and at the same time, a forward voltage is applied via the word line to lower the potential barrier and write is performed. In this case, no data is written to memory cells to which no voltage is applied to the word line. If the channel section is in such a state that applying a positive voltage to the bit line is enough to cause electrons to flow out from the source (b), then the word line can be passed through the gate of the memory cell to which data is not written and the reverse direction is applied. All you have to do is apply voltage. In case (a), data can be read by applying a forward voltage (positive voltage in this example) to the word line, or by returning it to the O voltage if it was biased in the reverse direction.
3 flows into the source 11 which is in a positive potential state, and whether or not data is accumulated is detected based on the presence or absence of current at that time. In other words, the channel is opened and conduction occurs between the source and drain, so that the potential of the source region is read out to the outside. Figure 1b,
In structure c, when electrons flow out from the source region 11 and the potential of the source region increases, the depletion layer extending from the source region 11 to the substrate 15 side gradually expands, the storage capacitance C decreases, and the source The potential Q/C with respect to the amount of charge Q charged in the region suddenly increases. If such a change in potential is undesirable, a high resistance region 19 may be inserted between the source region 11 and the substrate 15, as shown in FIG. 1d. In this example, the high resistance region 19 is a P ^- layer, but it may also be an N ^- layer, and the impurity density and thickness are selected so that the diffusion potential of the source region 11 and the substrate 15 forms a depletion layer. In this way, the storage capacitance C is kept constant regardless of the potential of the source region, and the potential of the source is simply given by Q/C with respect to the charge Q flowing out from the source. Of course, it is also effective to provide an impurity distribution between the source region 11 and the substrate 15 so as to cause a desired potential change with respect to the amount of charge flowing out from the source. In FIG. 1d, an isolation n region 20 is provided between the gates of each memory cell. This is to prevent punch-through current from flowing between the gates of adjacent memory cells.If punch-through current flows between the gates of adjacent memory cells, this isolation region 20 Just insert . A memory cell much the same in operation as described above can also be constructed with a bipolar transistor whose base is mostly or completely punched through. An example of this is shown in
Shown in Figure e. It has already been shown in Japanese Patent Application No. 52-15879 "Semiconductor Device and Semiconductor Integrated Circuit" that a bipolar transistor whose base is almost in a punch-through state operates in a manner similar to SIT.
No. 17327, ``Semiconductor Integrated Circuits,'' as detailed above. ^P-
When the impurity density of the region 14'' is sufficiently low and its thickness is sufficiently thin, the operation will be as described in (b) above, and when the impurity density of the P ^- region is high or thick, the operation will be as described in (a) above. This is the behavior in the case of .

In the embodiment shown in FIG. 1, the potential is not too high due to considerations such as preventing punch-through current from flowing between the substrate and the gate and ensuring that the charges accumulated in the source region are retained for a sufficiently long time. There is a restriction that cannot be given to each area. Furthermore, the gate capacitance is large, and the word line capacitance becomes large, which may impede speeding up.

In SIT memory, it is also possible to create a memory in which a MOS capacitor is provided on the surface of the semiconductor, instead of providing a storage capacitor between the floating region buried inside the semiconductor and the substrate as in the example shown in Figure 1. . of this type
SIT memory also has punch-through current issues,
There is a drawback that high speed performance is reduced due to an increase in word line capacitance due to a large gate capacitance.

SUMMARY OF THE INVENTION An object of the present invention is to overcome these drawbacks and provide a semiconductor memory in which a desired potential can be applied to each region, and the word line capacitance can be reduced to enable high-speed writing and reading.

Hereinafter, the present invention will be explained in detail using the drawings.
FIG. 2 shows a specific example of the present invention. Figure 2 a is
Plan view, Figure 2b is a sectional view along line AA', Figure 2b is
FIG. 2c is a sectional view taken along line BB', and FIG. 2d is another sectional view of the memory cell of the present invention. Figure 2b,
As is clear from the cross-sectional view in FIG. By introducing the region 14'', no punch-through current flows between the gates of adjacent memory cells and between the gate 14 and the substrate 15. At the same time, because it has a medium-sized gate structure in which channels that exist concentrically outside are controlled by the gate 14 that exists inside, the gate capacitance is reduced, and the word line capacitance is also reduced, further increasing speed. It will be done. The gates of each memory cell are connected by a wiring 14' made of metal such as Al or Mo or low resistance polysilicon to form a word line. Similarly, the drain 13 of each memory cell is connected by a metal 13' such as Al or Mo to constitute a bit line. The write, store, and read operations and the impurity density dimensions of each region are almost the same as described with respect to FIG. A storage capacitor is formed between the floating region 11 and the substrate 15. The dimensions of the floating region and the impurity density of the substrate are chosen such that the storage capacitance is the desired value, for example 0.18PF. To achieve a capacitance of 0.18PF at a write voltage of, say, 10V in a memory cell with a diameter of approximately 23μm, the impurity density of the substrate must be 1×10 ¹⁷ cm.
It should be around ^-3 . In addition, in the memory shown in FIG. 2, each memory cell can be arranged compactly, the insulating layer 16 is made thick, and the drain 13 is made as thin as possible (for example, 0.3 μm or less) and separated from the adjacent P regions 14 and 14''. In this way, the bit line capacitance of conventional memory can be reduced to about 1/10, so the storage capacitance is only 0.018pF, and the size of the memory cell is about 7μmφ.In this medium-sized structure memory cell, the outer isolation gate is connected to each It constitutes the isolation region of the memory cell, and has extremely high area efficiency.Furthermore, compared to the one shown in FIG. 1, it is easier to increase the storage capacity.

FIG. 2d shows another embodiment of the present invention, in which a drain contact electrode 13' is provided over the entire drain region 13.

In the medium-sized gate structure shown in FIG. 2, since a wide channel can be effectively controlled with a small gate, the conversion conductance gm is large, the word line capacitance is extremely small, and the speed is increased.

In order to reduce the bit line capacitance, make the memory cell smaller, and improve the degree of integration, it is necessary to reduce the thickness of the insulating layer 16 and the drain region 13, as well as the P ⁺ region 14 and the P region 14. It is effective to configure the drain region away from the drain region. Even if the drain region is made small, the current is focused, so it has almost no effect.

FIG. 3 shows another embodiment of the invention with a MOS structure storage capacitor on the surface. 3a and 3b are cross-sectional views taken along lines AA' and BB', respectively, in the case of a memory cell having a concentric configuration similar to that shown in FIG. 2a. The bit line 23 is constituted by an n ⁺ region 23 buried inside the semiconductor. The storage capacitor is formed between the n ⁺ region 21 and an electrode 21' made of metal such as Al or Mo, low resistance polysilicon, or a combination of these. Writing is performed by applying a positive voltage to the bit line 23 when a positive voltage is applied to the word line 14' to make the channel conductive. n ⁺ area 21
Electrons flow from the bit line to the bit line, and the region 21 becomes positively charged. When the positive voltage on the word line is removed, this charged state is maintained. This charged state can be read externally by applying a positive voltage to the word line to make the channel conductive. In order to reduce the capacitance of the bit line 23, it is possible to insert a high resistance region (n ^- , P ^- or i region) between the bit line 23 and the substrate, or to separate the P region 14'' and the bit line a little. Good. The insulating layer above the n ⁺ region 21 is made thin to increase storage capacitance, for example 100 Å to 1500 Å. Other parts of the insulating layer are made thick to reduce word line capacitance. For example, it is 3000 Å to 2 μm.

The embodiments shown in FIGS. 2 and 3 are specific examples of the semiconductor memory of the present invention, and it goes without saying that the present invention is not limited thereto. Even a device with a structure in which the conductivity type is completely reversed will operate in the same way if the polarity of the applied voltage is reversed. Further, although all gates are shown as junction type, gates are not limited to junction type, and may be of any type that exhibits rectifying properties, such as Schottky type, MOS/MIS type, etc.

Moreover, as a specific example, although the semiconductor memory of the present invention has mainly been described using SIT, it goes without saying that a field effect transistor (FET) may also be used. Two main electrodes are configured three-dimensionally, one of which is a floating region inside or on the surface of the semiconductor, and the inflow and outflow of carriers between the two main electrodes is controlled by a medium-sized gate electrode, that is, a medium-sized control electrode. , any memory cell may be used as long as each memory cell is separated by a channel and a region of an opposite conductivity type.
Although the structure of the channel is limited to a concentric one in the drawings, it may be of any shape such as a rectangular shape, a directional shape, an ellipse shape, or a striped shape. The floating electrode is provided inside as shown in Fig. 2, and the contact electrode of the main electrode on the surface may be provided in a part as shown in Fig. 2c.
It may be provided over the entire surface as shown in FIG. 2d. In the case of FIG. 3 in which the main electrode on the front surface is made into a floating region, a MOS capacitor is provided over the entire surface, but it goes without saying that a portion may be provided.

The structure of the embodiment of the present invention can be easily manufactured by making full use of conventionally known techniques such as selective growth, selective diffusion, ion implantation, microfabrication, selective etching, plasma etching, sputtering, thermal oxidation, and CVD.

The semiconductor memory of the present invention uses bulk conduction,
Moreover, since the carrier movement is performed by an electric field, the read/write speed is fast, and the three-dimensional structure allows for large capacity, and since each memory cell is separated by a channel and a region of the opposite conductivity type, the operating voltage There are few restrictions on the selection of gates, and since the gate structure is medium-sized, the word line capacitance is reduced and extremely high-speed operation can be performed, and its industrial value is extremely high.

[Brief explanation of the drawing]

Figure 1 a to f are conventional SIT memories, Figure 2 a
3a to d are semiconductor memories of the present invention; FIGS. 3a to 3b
is a semiconductor memory of the present invention.

Claims (1)

[Claims] 1. Two main electrodes made of high impurity density regions of the same conductivity type are provided on the surface and inside of the semiconductor, respectively, substantially perpendicular to the semiconductor surface, and one of the two main electrodes is used as a floating electrode, A potential barrier existing between the two electrodes is to be controlled by a medium-sized structure control electrode made of an impurity region of opposite conductivity type and a separation region provided between the memory cell, and a word column line made of the control electrode and the main electrode. A semiconductor memory characterized in that the memory cell is included in at least some of the intersections of a matrix made up of connected bit row lines and matrix lines. 2. Claim 1, characterized in that the main electrode provided on the semiconductor surface is a floating electrode, and an electrode is provided on the floating electrode via an insulating layer.
Semiconductor memory described in Section 1. 3. The semiconductor memory according to claim 1, wherein the main electrode provided inside the semiconductor is a floating electrode, and the main electrode provided on the surface of the semiconductor is connected to a bit line. 4 The control electrode may be a junction type, a shot key type,
The semiconductor memory according to claim 1, characterized in that it is an MIS type electrode.