JPS6161292A - メモリ装置 - Google Patents

メモリ装置

Info

Publication number: JPS6161292A
Authority: JP; Japan
Prior art keywords: memory; data; comparators; comparison; input
Prior art date: 1984-09-03
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Granted

Application number

JP59184326A

Other languages

English (en)

Japanese (ja)

Other versions

JPH0557678B2 (fr

Inventor

Hideki Nishimori

西森　英樹

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

NEC Corp

Original Assignee

NEC Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1984-09-03

Filing date

1984-09-03

Publication date

1986-03-29

1984-09-03 Application filed by NEC Corp filed Critical NEC Corp

1984-09-03 Priority to JP59184326A priority Critical patent/JPS6161292A/ja

1986-03-29 Publication of JPS6161292A publication Critical patent/JPS6161292A/ja

1993-08-24 Publication of JPH0557678B2 publication Critical patent/JPH0557678B2/ja

Status Granted legal-status Critical Current

Links

230000015654 memory Effects 0.000 title claims abstract description 49
230000000295 complement effect Effects 0.000 claims abstract description 10
230000003247 decreasing effect Effects 0.000 abstract 1
238000010586 diagram Methods 0.000 description 3
238000007493 shaping process Methods 0.000 description 3
238000003491 array Methods 0.000 description 1
230000000694 effects Effects 0.000 description 1
230000010365 information processing Effects 0.000 description 1
238000004519 manufacturing process Methods 0.000 description 1
239000004065 semiconductor Substances 0.000 description 1
230000008054 signal transmission Effects 0.000 description 1

Landscapes

Static Random-Access Memory (AREA)

JP59184326A 1984-09-03 1984-09-03 メモリ装置 Granted JPS6161292A (ja)

Priority Applications (1)

Application Number	Priority Date	Filing Date	Title
JP59184326A JPS6161292A (ja)	1984-09-03	1984-09-03	メモリ装置

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP59184326A JPS6161292A (ja)	1984-09-03	1984-09-03	メモリ装置

Publications (2)

Publication Number	Publication Date
JPS6161292A true JPS6161292A (ja)	1986-03-29
JPH0557678B2 JPH0557678B2 (fr)	1993-08-24

Family

ID=16151365

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
JP59184326A Granted JPS6161292A (ja)	1984-09-03	1984-09-03	メモリ装置

Country Status (1)

Country	Link
JP (1)	JPS6161292A (fr)

1984
- 1984-09-03 JP JP59184326A patent/JPS6161292A/ja active Granted

Also Published As

Publication number	Publication date
JPH0557678B2 (fr)	1993-08-24

Similar Documents

Publication	Publication Date	Title
US6804743B2 (en)	2004-10-12	Two step memory device command buffer apparatus and method and memory devices and computer systems using same
US6385128B1 (en)	2002-05-07	Random access memory having a read/write address bus and process for writing to and reading from the same
US6392910B1 (en)	2002-05-21	Priority encoder with multiple match function for content addressable memories and methods for implementing the same
US9385032B2 (en)	2016-07-05	Systems and methods involving data bus inversion memory circuitry, configuration and/or operation
US4712190A (en)	1987-12-08	Self-timed random access memory chip
US6845024B1 (en)	2005-01-18	Result compare circuit and method for content addressable memory (CAM) device
JPS635839B2 (fr)	1988-02-05
US6538952B2 (en)	2003-03-25	Random access memory with divided memory banks and data read/write architecture therefor
US6223260B1 (en)	2001-04-24	Multi-bus data processing system in which all data words in high level cache memories have any one of four states and all data words in low level cache memories have any one of three states
US5361230A (en)	1994-11-01	Memory device delaying timing of outputting data in a test mode as compared with a normal operating mode
US6542569B2 (en)	2003-04-01	Memory device command buffer apparatus and method and memory devices and computer systems using same
EP1494243B1 (fr)	2013-05-01	Système mémoire avec inversion de données et méthode d'inversion de données pour système mémoire
US6262936B1 (en)	2001-07-17	Random access memory having independent read port and write port and process for writing to and reading from the same
US4473877A (en)	1984-09-25	Parasitic memory expansion for computers
JP3655329B2 (ja)	2005-06-02	キャッシュタグメモリ
US20040264275A1 (en)	2004-12-30	Precharge apparatus in semiconductor memory device and precharge method using the same
JP3604861B2 (ja)	2004-12-22	半導体記憶装置
US7346731B2 (en)	2008-03-18	High performance and scalable width expansion architecture for fully parallel CAMs
JPS6161292A (ja)	1986-03-29	メモリ装置
KR102795672B1 (ko)	2025-04-15	데이터 정렬 제어 회로 및 이를 포함하는 메모리 장치
US6353548B2 (en)	2002-03-05	Method and data processing system for data lookups
US6014333A (en)	2000-01-11	Semiconductive memory device capable of carrying out a write-in operation at a high speed
JP3740312B2 (ja)	2006-02-01	Ｃａｍセル回路
US6580628B2 (en)	2003-06-17	Associative memory
JP3923642B2 (ja)	2007-06-06	半導体記憶装置

Legal Events

Date	Code	Title	Description
2004-09-03	EXPY	Cancellation because of completion of term