JPS6161425B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a data processing integrated circuit device, and more particularly to the structure of an integrated circuit device that includes a read-only memory (hereinafter referred to as ROM) for storing programs on the same chip. Since an integrated circuit device having an internal program storage ROM is not limited by the word length per instruction, the instruction code can be set with a longer number of bits than the word length for data transfer with the outside. Therefore, it is possible to set advanced instructions in one instruction code, which has the advantage of increasing the sophistication and speed of processing. On the other hand, in an operation confirmation test (hereinafter referred to as a test), it is advantageous for this type of device to conduct a code check test of the ROM part in the chip and a function test of other execution unit parts separately. This is because the execution units that perform functional tests (logic gates used for ALU and other processing) have roughly the same circuit design in each device to ensure versatility.
At least one type of test pattern is sufficient, but the contents of the ROM section vary depending on the user's program. Therefore, the ROM section and execution unit section are
If you want to test using ROM instruction codes, you will have to prepare different test codes for all types of products with different ROM contents.
In this regard, if the ROM part and the execution unit part are tested separately, the test pattern for the execution unit part can be common to each product, and the instruction code for the ROM part can be used as well. Since it is only necessary to read out the data externally and test it, it has the effect of significantly reducing test time and costs. Therefore, it is desirable to adopt the above-mentioned test method for the above-mentioned integrated circuit device. However, there are drawbacks to adopting this test method as described below. In other words, a data processing integrated circuit device with a built-in ROM (hereinafter referred to as a 1-chip microcomputer)
Since there is no means for setting instruction codes from the outside, test patterns are input to the execution unit using data input/output terminals. on the other hand,
A 1-chip microcomputer with built-in ROM is 1
Since it is possible to take a large number of bits per instruction, one instruction is divided into multiple blocks, a decoder is set up for each block, and the decoder output (control signal) is used to independently control the block execution units. It can be used as a so-called horizontal micro-instruction type. However, since test patterns cannot be input to each decoder from the outside at the same time, the entire execution unit section cannot be inspected with one test pattern input, and the test processing time is extremely long. There were flaws. An object of the present invention is to provide an integrated circuit device for data processing in which data setting time and test processing time are shortened by adding a new data input means. According to the present invention, a plurality of registers can store data input from the outside by applying a control signal, and a control section that applies the control signal to the plurality of registers at the same timing. An integrated circuit device for data processing is obtained. Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of this embodiment, which has a ROM1 for storing microinstructions, and one instruction code read from this ROM1 is divided into, for example, three blocks and transmitted via corresponding signal lines 21 to 23. Dedicated instruction disassociator (decoder) for each readout
2, 3, and 4 are input. The execution unit section 18 to which this decoder output is supplied as a control signal,
Each of the decoders 2, 3, and 4 is divided into independently controlled blocks, each of which executes a program process specified by a control signal. Further, processing results and data necessary for processing are led out or introduced to an external data input/output terminal 6 via an internal bus 5. On the other hand, three registers 7, 8, and 9 are commonly connected to this internal bus 5, and their outputs are input to opposing decoders 2, 3, and 4 via switching circuits 10, 11, and 12. I'm also getting used to it. Data input control to registers 7 to 9 is as follows:
This is performed by input control signals 15 to 17 from the control section 13, and the switching control of the switching circuits 10 to 12 is also performed by the switching signal 14 from the control section 13. Here, the control unit 13 registers 7 to 9.
It is desirable to have a function of independently generating the input control signals 15 to 17, and a function of generating them simultaneously. This can be realized, for example, by configuring the circuit with a circuit function as shown in FIG. Second
Referring to the figure, signals 19, 20, and 14 are input signals, and signals 15 to 17 (corresponding to the input control signals in FIG. 1) are output signals. ,as well as
The input signal 20 is input to the AND gate 25.
It is input to AND gate 24, NOR gate 27, and AND gate 26. Furthermore, AND gate 24 and NOR
Output with gate 27 is via RO gate 28
It is input to AND gate 29. AND gate 2
Each of the other input terminals 9, 25, and 26 receives the control signal 1.
4 are input, and each of their outputs is an input control signal 1
5 to 17 are supplied to registers 7 to 9, respectively. Now, Table 1 shows the true value table of the input and output of the control section 13 shown in FIG.

[Table] As is clear from Table 1 above, when testing the execution unit section, for example, if the signal 14 is set to the "1" level, registers 7 to 9 can be set by appropriately selecting input signals 19 and 20. On the other hand, test patterns input from the terminals 6 can be set independently, or test patterns can be set simultaneously in common to each register. More specifically, for example, in a normal program processing process, the switching circuit 10
-12 are controlled so that the signal lines 21-23 and decoders 2-4 are connected, then the instruction code read from ROM1, for example 24 bits as one byte, is input to the decoder 8 bits at a time. is,
It is decoded and becomes a control signal to the execution unit section 18. On the other hand, during testing, a code check can be performed by connecting the ROM 1 to the internal bus and reading the instruction code to the outside in three 8-bit blocks. Further, when checking the execution unit section 18, the execution unit section 18 can be tested at the same time by inputting an 8-bit test pattern from the terminal 6 and inputting it to the registers 7-9 at the same time. Incidentally, during testing, even if the same test pattern is set in each register 7-9, the execution unit section can be tested. If it is desired to test each execution unit block with different test patterns, the input signals to the control section 13 may be specified so that the input control signals 15 to 17 are generated independently. As a result, whereas conventionally it was impossible to set input data to multiple registers at the same time, in this embodiment it is possible to set external input data to multiple registers at the same time. It was possible to significantly reduce the time and test processing time. Note that the control of the registers 7 to 9 can be sufficiently applied not only during testing but also during normal program processing, such as when inputting an instruction code from the outside, and can improve program processing efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing integrated circuit device showing one embodiment of the present invention, and FIG. 2 is a logic circuit diagram showing one embodiment of the control section thereof. 1...ROM, 2-4...decoder, 5...internal bus, 6...data input/output terminal, 7-9...register, 10-12...switching circuit, 13...control unit, 14... Switching signal, 15-17... Input control signal, 18... Execution unit section, 19, 20...
Input signal, 21-23...signal line for instruction code,
24-26, 29...AND gate, 27...
NOR gate, 28...OR gate.

Claims (1)

[Scope of Claims] 1. A storage unit storing an instruction code, an input unit for externally inputting information with a bit length shorter than the instruction code, a bus connected to the input unit, and a bus common to the bus. a plurality of storage blocks connected to the bus, each having a capacity to temporarily store the information; a control means for storing information from the outside transferred to the plurality of storage blocks through the bus; and an instruction comprising a plurality of blocks. a decoder; means for selecting whether to input an instruction code in the storage unit or information in each storage block to each block of the instruction decoder; means for supplying the instruction code or the information; and an execution unit that executes processing based on the instruction code when the instruction code is selected, and executes processing based on the information when the information is selected. An integrated circuit device comprising: 2. The control means has a circuit that selectively generates a timing signal for inputting the externally input information into each of the storage blocks separately and a timing signal for simultaneously inputting the information to each of the storage blocks. An integrated circuit device according to claim 1, characterized in that: