JPS6162149A - Memory control device - Google Patents

Abstract

PURPOSE:To obtain a memory control device which can improve the dynamic modification of system constitution by processing normally a memory access from an input/output control device while cache memory data are discharged to the main memory device. CONSTITUTION:When a memory access is carried out from a arithmetic control device 301 or an input/output control device 401 to a memory control device 101, request information such as an action designition cord, address and stored data is received by a request receiving port circuit 110 or 111. Thereafter, a request data is selected by the request receiving port circuit to send the information to a stage 1 request register 112, where the interpretation of the action designation corcd in executed and the action in accordance with the next action designation are carried out. When the action designition is a read request, an address array 130 is retrieved to investigate whether the required data exist on a cache memory or not. When they exist, corresponding data is read out from a cache memory 131 to a data register 118 and sent.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a memory control device, and particularly to a means for discharging cache memory data to a main memory device in a memory control device equipped with a set-associative type and store-swap type keyed memory. It is related to.

(Prior Art) In large-scale information processing systems, the processing speed of the memory element for the main memory device has not been improved relative to the improvement in the processing speed of the arithmetic and control unit. In order to absorb the difference in processing speed between the two, there is a system in which a store swag type cache memory is installed within the memory control device to shorten the average memory access time and improve the load on the main memory device. In a system with only a store-swag type cache memory, the latest memory data exists on the main memory device during operation, but in a system with a store-swag type cache memory, depending on the memory data, the latest memory data exists on the main memory device. It may exist only in the cache memory. Such non-currentness of main memory device data poses a major hindrance to dynamic changes in logical connections between devices in the system configuration.

The system configuration of the memory control device is shown in FIGS. 1 to 3 as examples of connections between each device. Mesosu control device 10
1 and 102 are connected to the main memory devices 201 to 204, and further connected to arithmetic and control units 301 and 302 and input/output control units fi 401 and 402, respectively. Solid lines between devices indicate that they are logically and physically connected, and broken lines indicate that they are physically connected but logically disconnected. are logically connected and operated as a so-called multiprocessor. The system shown in Figure 2 is a system with two
Both are operated independently as the Dugrex system. In the system shown in FIG. 3, the memory control device 102 is disconnected due to a failure or the like. It is desirable that state changes between these system configurations be performed without affecting users who are using the system. Particularly when the system is used online, impacting end users must be avoided.

In a system having a store swag type cache memory in the memory control devices 101 and 102, FIGS.
As shown in the figure, a configuration is generally adopted in which only one memory control device is logically connected to one main memory device.

As a result, even if the data in the main memory device is registered in the cache memory in the memory control device to which this main memory device is logically connected, the data in the main memory device is stored in the cache memory in the memory control device to which it is logically not connected. (The data between the cache memories is exclusive, and there is no need to control data interference between the two.)

In such a configuration, for example, when transitioning from the system configuration of FIG. 3 to the system configuration of FIG. 1, the main memory device 203 logically connected to the memory control device 102 after the transition
, 204 exists on the cache memory in the memory control unit 101, simply switching the logical connection relationship will not allow normal memory access to the main memory units 203 and 204 after system configuration migration. .

The following method can be used to transition from the system configuration shown in FIG. 3 to the system configuration shown in FIG. 1 without inconsistency in the latestness of memory data.

The first method is to stop the system once, change the logical connections between devices, and then restart the system by initializing the system (main memory data continuity is not required). In this case, it takes a lot of time to complete the restart after stopping, which has a large impact on the users who are using the system.

The second method is to suspend the processing of the arithmetic control units 301 and 302 at instruction breakpoints, prevent the start of new input/output operations, and then control the memory once the currently executing input/output operation is completed. The cache memory data in the device 101 is written out to the main memory device. Upon completion of this writing, the data in the main memory devices 203 and 204 will be in the latest state. Thereafter, the logical connection relationship between the devices is changed and processing is restarted while maintaining the continuity of the main memory data.

Although this method does not have a negative impact on the user compared to the first method, it may have a large impact on the user because it requires a lot of time to wait for the input/output operation currently being executed to stop. .

The third method is to stop and suspend the processing of the arithmetic control units 301 and 302 at the command break, and to inhibit and suspend the memory access processing in the memory control unit ff1lo1 while the input/output processing is in progress. When memory access is suppressed, the cache memory data in the memory control device 101 is flushed out to the main memory device, and when the flushing is completed, the logical connection relationship between the devices is changed to ensure continuity of the main memory data. Restart processing while maintaining the status.

With this method, there is no problem with the system stopping from the user's point of view during the time it takes for the cache memory data to be flushed to the main memory device, but command overload due to memory access processing inhibition of input/output processing during the flushing of the cache memory data is not a problem. Runs and Data Oats - There is a risk that the occurrence of multiple runs will not be able to be brought under control.

If the arithmetic processing unit to the cache memory could perform the process of writing out the cache memory data to the main memory unit while normally processing memory access from the input/output device, the above method would not be necessary. Processing problems occur when there is a memory access to cache memory data that has already been written to the main memory device.

Similar processing can be applied to the transition between the system configuration in FIG. 1 and the system depiction in FIG. 2. Therefore, the conventional memory control device system has the disadvantage that there is no means for effectively changing the system configuration.

(Object of the Invention) An object of the present invention is to eliminate the drawbacks of conventional memory control devices, and also to eliminate the last row of the cache memory in the store-swap type cache memory data flushing process in the memory control device onto the main memory. Until the start of the flushing process, new block allocation at the time of a cache memory miss is limited to only unextracted rows, and when there is a cache memory miss in the memory access during the last row flushing process, the already flushed rows are canceled. Provided is a memory control device that can be used as a data buffer for email bypass processing to avoid inhibiting memory access of an input/output control device while flushing data from a cache memory, and improve dynamic change processing of system configuration. It's about doing.

(Structure of the Invention) According to the present invention, a plurality of arithmetic control devices, a plurality of input/output control devices, a plurality of main memory devices, and a memory access request to the main memory device from the arithmetic control devices and the input/output control device are transmitted. In an information processing system including a plurality of intervening memory control devices, each of the memory control devices having a cache memo of a set ancillary type and a store swap type that is shared by each of the arithmetic control units and input/output control units. , means for specifying a line in the cache memory and prohibiting new block registration to the line; and means for specifying a line in the cache memory and discharging data in the line to the corresponding main memory device; Even when data corresponding to a memory access to the memory control device does not exist in the cache memory, new registration is not performed in the address array in which the chime information of the cache memory is stored, and the memory access is written. performing a block transfer of block data from the main memory device to the cache memory to which write data yields when a request is made to one of the rows in which the flushing has been completed, and after the block transfer operation is performed, the writing A memory control device is provided, comprising means for writing a block of the block-transferred data including data into the main memory device.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 shows an embodiment of the present invention. In FIG. 4, one embodiment of the present invention is connected to an arithmetic control device 301 and an input/output control device 401, further connected to a main memory device 201, and shared by each of the arithmetic control devices and input/output control devices. In a memory control device 101 having a cache memory of a set-anonymous type or a store-swap type, specifying a row of the cache memory,
a circuit 119 that prohibits new block registration to the row; an output control circuit 123 that specifies a row in the cache memory 131 and outputs data of the row to the corresponding main memory 1J device 201; and means for transferring data to memory 131 and writing blocks to the main memory device.

Furthermore, this memory control device 101 has a request receiving port circuit 111 .connected to the input/output control device 401 .
126 , request reception port circuits 110 and 127 connected to the arithmetic and control unit 301 , and an output column address counter 122 connected to the output control circuit 123
and the request reception port circuits 110, 111, 1
26, 127 and exposed column address counter 122
a stage 1 request register 112 connected to;
It includes a stage 2 request register 113 connected to the stage 1 request register 112 and a stage 3 request register 114 connected to the stage 2 request register 113 and whose output is further connected to the main memory device 201.

The stage 1 request register 112 is connected to the input data register 115, the address array 130, and the address comparison circuit 121, and is further connected to the row designation new allocation prohibition bit 119, the output control circuit 123, and the input/output control device request reception inhibition. Connected to bit 124. The row designation new allocation prohibition bit 119 is connected to the regression circuit 132. The output control circuit 123 is connected to the arithmetic control device, and the input/output control manufacturing request reception suppression bit 124 is connected to the input/output control device 4.
01.

The write data register 115 is connected to the read data selection circuit 125.
and a cache memory 131. The address array 130 is connected to an address array data selection circuit 117 via an address array register 116.

Stage 2 request register 113 is connected to cache memory 131 and replacement circuit 132.

Stage 3 request register 114 is connected to main memory request buffer 120 and stage 1 request register 1.
12. Furthermore, main memory request buffer 120 is connected to cache memory 131, write data register 115, and stage 1 request register 112. Cache memory 131 is connected to read data selection circuit 125 and main memory device 201 via read data register 118. Read data selection circuit 125 is connected to select either write data register 115 or read data register 118 and supply the selected data to arithmetic control device 301 and input/output control device.

Next, an example of the operation in the memory control device 101 for memory access will be described. Memory access from the arithmetic control device 301 or input/output control device 401 is performed by the memory control device 10.
1, the request information such as the operation designation code, address, and store data is received at the request reception port DO path 110 or 111. Next, one piece of request information is selected from the request reception port circuit and sent to the stage 1 request register 112.

The stage 1 request register 112 decodes the operation designation code, and performs the operation according to the next operation designation. When the operation designation is a read request, the address array 130 is first indexed to check whether or not the required data exists on the cache memory. When it exists (cache memory I', !: call), the corresponding data is read from the cache memory 131 to the translated data register 118 and sent to the requesting device. Further, the referenced cache memory block is reflected from the stage 2 request register 113 to the placement circuit 132.

The operation specification is a write request, and the address array 130
If the corresponding data exists in the cache memory as a result of the index, the corresponding data in the cache memory 131 is read from the write data register 115. Writing to main memory device 201 is not performed at this time. At this time, the information is reflected to the replacement circuit 132 in the same way as when reading. By the way, when a modification bit corresponding to a cache memory block in the address array 130 is on, it indicates that the latest data of the corresponding block is not present in the main memory device 201 but exists only in the cache memory 131. Qualification bits must be turned on when a write is performed. When a write request exists and corresponding data exists on the cache memory, the data in address array 130 is read to address array register 116 and the value of the modification bit is examined. When this qualification bit is off, the write request information is stored in stage 3 request register 1141i! The data is output and returned to the stage 1 request register 112, and a registration operation is performed in the address array 130 to turn on the modification bit of the corresponding block in the address array 130.

When the required data does not exist on the cache memory as a result of address array 130 index in a read request or a write request (referred to as a memory miss), the following operation is performed. In the stage 2 request register, rig 1. - The instrument circuit 132 is accessed and the row number of the block to be newly allocated is determined.

This row number indicates the address array register 11 in which the data read from the address array 130 is stored.
The address array data of the block to be replaced from stage 3 is selected by the address array data selection circuit 117 and becomes part of the data in the stage 3 request register 114. Information in the stage 2 request register 113 is also sent to the stage 3 request register. stage 3
A block transfer request is issued from the request register 114 to the main memory device 201, and request information in the request to the main memory device is stored in the main IJ quest buffer 120. The types of this request information include the column address and row address of the cache memory to which the block transfer booter should write, and store data when the request from the request source is a write request. The contents of stage 3 request register 114 are returned to stage 1 request register, and new allocation block information is registered in address array 130. When the request from the request source is a read request, the modification bit is turned on at the same time. When the qualification bit of the block of the replaced address array is on, the latest data of the block to be replaced does not exist in the main memory device 201, but exists only in the corresponding block of the cache memory 131, so this data must be returned to main memory. At this time, the request information in the stage 1 request register 112 including the address of the replaced block is stored in the stage 2
It is sent to the request register 113 and further stage 3
A block swallow request is made to the main memory device 201 using the address of the replaced block from the request register 114. Main memory device ff1201 at this time
The write data to the cache memory 131 is sent via the read data register 118. When the request from the request source is a read request, when the block transfer data is read from the main memory device 201, the data is stored in the write data register 115. At this time, the row address of the cache memory where the above data should be written from the main memory request buffer 120,
The column address is taken out, and the data in the write data register 115 is written into the cache memory 131. Further, the data is sent to the request source via the read data selection circuit 125. When the request from the request source is a write request, the main memory request buffer 12 receives block transfer data from the main memory device 201.
Store data is taken out from 0, merged with the block transfer data, and placed in the scooped data register 115.

In the above request processing, since a plurality of requests are processed in a pipeline manner, address interference occurs between request processings, but an address comparison circuit 121 is provided to avoid this. The address that is currently being processed is stored in the address comparison circuit, and this address is compared with the address that has newly entered the stage 1 request register 112. If they match, the address in the stage 1 request register 112 is compared.
Request processing of the request register 112 is suppressed.

Examples of address interference include the following cases. If a memory access to the same block is performed while a cache memory miss is being processed for a certain block, the former process will be performed by the address array 130.
If it is before registration, the latter will also result in a cache memory miss and a block transfer request to the same block will be issued to the main memory device 201. The latter fails to process a cache memory hit even though the data is not finalized in the memory 131.As another example, while processing a cache memory miss for a certain block, an additional block, although not in the same program, is processed. When there is a memory access to the same column address and the latter is a cache memory miss, there is a possibility that the latter may replace the former block being processed depending on the case.

In the set ancillary system, this problem does not occur if the column addresses are different.

In order to repair the rear side, the address comparison circuit 121 compares not all addresses but the data 11 address portion.

Next, a description will be given of how cache memory data is written to the main memory device when the system configuration is dynamically changed in one embodiment of the present invention.

In this embodiment, the following individual operation functions are provided in the memory control device, and each function is realized by microinstruction control of an arithmetic control device or the like.

Function 1 is the line specification new allocation prohibition bit 1191. .

It is. This prohibition bit is provided corresponding to each row of the cache memory, and can be set or canceled by the request source HC. When this prohibition bit is set, it is prohibited to use the corresponding line as a target for replacement in the event of a cache memory miss.

However, when it is a cache memory bit, read/write access to the corresponding row is permitted.

In general, many cache memory devices are equipped with a degrade bit corresponding to a row for the purpose of separating faulty cache memory in units of rows, but this degrade bit prevents the corresponding row from being targeted for braces and prevents the cache memory from being targeted for braces. In contrast to the hit inhibition, the row-specified new allocation prohibition bit performs only the former operation.

The second function is the function of writing cache memory data in line units to the main memory device. This row-by-row printing operation is instructed by a request from a request source, and is controlled by a printing control circuit 123 and a printing column address counter 122. When a row printing request is received from a request source, the printing control circuit 123 is activated and the printing column address counter 122 is initialized.

When the column address of the output column address color/reference circuit 122 and the row address specified by the request source are sent as an output request to the stage 1 request register 112 and accepted, the column address of the output column address comparison circuit 122 is counted by +1, and then the needle is An output request is made to the stage 1 request register 112 using the column address. When the request to print all column addresses in the same row from the print column address counter 122 is accepted by the stage 1 request register, a row print completion report is sent from the print control circuit 123 to the requesting device that issued the row print request. When the stage 1 request register 112 receives the request, the specified row 9 of the address array 130 is
Perform column indexing. If the result of the index is that the valid bit or qualification bit of the block is off, the process ends there. The operation when the valid bit and the modification bit are on is that block transfer processing is not performed in response to the above-mentioned process when a cache memory miss occurs in normal memory access, and the effective Villain Tractor of the corresponding block in the address array 130 is turned off. The same operation is performed except for this point. This causes the latest data that is only on the cache memory to be flushed out to the main memory device.

The second function is cache memory miss processing that uses lines that have already been flushed out of the cache memory by specifying cache memory bypass. When a cache memory bypass designation request is sent from the request source, the cache memory bypass mode bit 126 is set. When this mode bit 126 is set and a memory access is received from a request source, the following operations are performed. When the memory access from the request source is the cache memory bit, the operation is the same as usual. When the memory access from the request source is a cache memory miss, a block transfer request is issued to the main memory device 201 as in normal times, but registration in the address array 130 is not performed. In addition, when registering request information to the main memory request buffer, normally the placement circuit 132 determines or enters a brace line address, but when the cache memory bypass mode pin l-12 (5) is on, line designation new The address of one of the rows for which the allocation prohibition mark 119 is set is entered.When a block transfer retry is returned from the main memory device 201, if the request from the request source is a read request, the address of one row is entered. The same operation is performed as in , but when the request -b=qp is included from the request source, the request information is sent from the main memory request buffer 120 to the stage 1 request register 112.From the stage 1 request register onwards, normally Request information is sent to the stage 2 request register 113 in the same way as when the block modification bit is on, and block write information is sent to the main memory device 201 from the stage 3 request register 114. A request is made to load the main memory device fi!2.
As for the write data to 01, the data in the cache memory 131 is sent via the read data register 118 as in the normal case. This write data is obtained by merging the block transfer data sent from the main memory device 201 with the store data sent from the request source, and ends up bypassing the cache memory and writing to the main memory device. The same thing will happen if you do it. When the memory control unit has a cache memory using the store swap method, the main memory device does not have the function of partially rewriting data in response to a write, but only has a block write function, so requests from the request source are partially processed. In the case of a write request to rewrite data, the above-mentioned operation is required.

When using empty lines in the cache memory as a data buffer as described above, even if a certain request is being bypassed due to a cache memory miss, the column address of the subsequent cache memory miss bit request will not be processed. If the column address of the request inside is different, parallel processing is possible without colliding with the cache memory block being used as a data buffer. When both have the same column address, the address comparison circuit 121 detects a column address match as in normal times, and the latter process is inhibited.

Next, an example of an operating hand when the arithmetic and control unit 301 executes a dynamic change from FIG. 3 to W to the system configuration shown in FIG. 1 by combining each of the above functions will be shown.

■ Setting O of the new allocation prohibition bit 119 of the cache memory row N of the memory control device 101 (assuming that the cache memory is composed of rows O to N) ■ Exporting the row of the cache memory row N of the memory control device 101 Instructions.

■ After completing row N of ■, set the new allocation prohibition bit for row N-1.

■ Cache memory row N-1 of memory control device 101
Directions for extruding lines.

The following operations ① and ② are repeated until the extrusion of row 1 is completed.

■ Setting the cache memory bypass mode bit 126 of the memory control device 101.

(2) Instructing to write out row 0 of the cache memory of the memory control device 101.

■ After finishing printing line 0 of ■, change the @ physical connections between devices as shown in Figure 1.

(2) Clearing the new allocation prohibition pit 119 from row N to row 1 of the memory control device 101 and canceling the cache memory bypass mode pit 126.

Memory control device 10 after system configuration change according to the above procedure
The data in the main memory devices 203, 204 logically connected to the main memory devices 203, 204 can be kept up to date. Third step of the above procedure
In the figure, the arithmetic control device 302 is also the memory control device 101.
If logically connected, the arithmetic and control unit 301 sends a processing suppression request to the arithmetic and control unit f302 via inter-device communication before step (3), and the memory control from the arithmetic and control unit 302 is Stop memory access to device f 101. Further, when a part of the row of the cache memory in the memory control device 101 is disconnected due to a failure state or the like, that row must be excluded from the extraction target in the above procedure.

(Effects of the Invention) As explained above, the present invention normally processes memory accesses from the input/output control device even while cache memory data is being written out to the main memory device, thereby creating a store swan within the memory control device. This has the effect of reducing problems associated with dynamic changes in system configuration in a system equipped with a cache memory of the type cache memory.

[Brief explanation of the drawing]

1, 2, and 3 are diagrams showing various system configurations in the memory control device, and FIG. 4 is a block diagram showing an embodiment of the invention. 101.102...Memory control device, 110,111
゜126.127...Request reception boat circuit, 1
12... Stage 1 request register, 113... Stage 2 request register, 114... Stage 3
'1) Request register, 115...Write data register, 116...Address array register, 117...Address array data selection circuit, 118
・Read data register, 119...Line specification new allocation prohibition pin), 120...Main memory request buffer, 1
2 door address comparison circuit, 122... Extrusion column address counter, 123... Exposure control circuit, 124...
・I/O control device request reception suppression pit, 125・
. . . Read data selection circuit, 126 . . . Cache memory bypass mode pit, 130 . . Address array, 131 . . Cache memo 'J, 132 .
・Main memory device, 301, 302... Arithmetic control device,
401.402...Input/output control device. 〆I苧w l ゛Representative Patent attorney Uchihara Al, Yan l Xiyan 2 Figure/I' 20/ 202 -fOJ
zUp true 4 figure

Claims (1)

[Claims] A plurality of arithmetic control devices, a plurality of input/output control devices, a plurality of main memory devices, and a plurality of memory access requests to the main memory device from the arithmetic control devices, the input/output control devices, and the input/output control devices. In an information processing system including a memory control device, each memory control device having a set associative type and store swap type cache memory shared by each of the arithmetic control units and input/output control units, means for specifying a line in the cache memory to prohibit new block registration in that line; means for specifying a line in the cache memory and flushing data in the line to the corresponding main memory device; Even when the registration information of the cache memory does not exist in the cache memory, no new registration is performed in the address array storing the registration information, and when the memory access is a write request, the block data to which the write data belongs is not registered. A block transfer from the main memory device to the cache memory is performed on one of the lines for which the flushing has been completed, and after the block transfer operation is performed, the block transferred data including the write data is transferred to the main memory device. 1. A memory control device comprising: means for writing a block to a memory controller.