JPS6165471A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce processes and give no restrictions to the acceleration voltage at the time of field ion implantation by a method wherein source, drain, and channel parts are patterned separately in an N type transistor and in a P type transistor. CONSTITUTION:An N-well region 2 is formed in a P type Si substrate 1. Thereafter, an Si oxide film 3 and an Si nitride film 4 are formed and patterned into each region of an N-channel TV. by using the technique of photo exposure. Next, with the mask of a resist pattern 5 and the nitride film pattern, field ions are implanted to a region 6 serving as the field part of the N type transistor. Further, the resist of each region of the P type transistor is patterned. With the mask of the resist pattern and the Si nitride film pattern, field ions are implanted to a region 7 serving as the field part of the P type transistor.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for manufacturing a CMOS type semiconductor device.

[Technical background of the invention and its problems]

As a method for manufacturing a CMOS type semiconductor device, for example, the method shown in FIG. 2 is known.

That is, as shown in Figure 2, Nwe is applied to a P-type Si substrate.
l Form a l area. Thereafter, as shown in FIG. 2(B), a silicon oxide film and a silicon nitride film are formed, a desired resist pattern is formed using a light exposure technique, and the silicon nitride film is etched using this as a mask.

Next, the resist pattern is peeled off, and the area where the P-type transistor number is to be formed is again covered with resist using light exposure technology. Using this resist pattern and the silicon nitride film pattern as a mask, the area that will become the field part of the N-type transistor is formed. , perform field ion implantation. (Figure 2 (C
)) Furthermore, the resist pattern is peeled off and N
The area where the P-type transistor will be formed is covered with a resist, and using this resist pattern and the silicon nitride film pattern as a mask, field ions are implanted into the region that will become the field part of the P-type transistor (Figure 2 (D)). The CNO8 semiconductor device is completed by peeling off and forming a gate oxide film, gate electrode, etc.

However, the conventional method has the following problems.

First, the number of light exposure steps is greater than in the case of manufacturing other semiconductor devices.

Therefore, in order to reduce costs, it was necessary to reduce the number of steps as much as possible.

2 (C) When performing field ion implantation,
) As shown in (D), there are parts where only the silicon nitride film serves as a mask, and if the acceleration voltage is set too high, ions will penetrate through the silicon nitride film and will be implanted in places where ions should not be implanted. There was something that happened.

[Summary of the invention]

In the present invention, patterning of the source, drain, and channel portions is performed separately in rows 9 for N-type transistors and P-type transistors.
characterized by things.

[Purpose of the invention]

In view of the above points, the present invention provides a CMO method that reduces the number of steps and does not impose restrictions on the acceleration voltage during field ion implantation.
The purpose of this invention is to provide a method for manufacturing an S semiconductor device.

〔Effect of the invention〕

According to the present invention, a CM that reduces the number of photoexposure steps, uses force, and does not impose restrictions on the acceleration voltage during the field ion implantation step.
o, 9 rate conductor device can be constructed.

The reasons for this are shown below.

P from pattern Jung of north, drain, and channel parts
In the conventional method, the number of light exposure steps required to complete the field ion implantation of the type transistor part and the N type transistor part is as follows. In contrast to the three ion implantations in the present invention,
Only two patterns, one for the N-type transistor and one for the P-type transistor, are required, and since ion implantation is performed after each pattern is completed, all areas where ion implantation is not performed are covered with resist. Therefore, there is no restriction on the accelerating voltage, which makes it possible to reduce the number of photo-exposure steps and eliminate the restriction on the accelerating voltage during field ion implantation, which were problems in the conventional method.

[Embodiments of the invention]

The present invention can be realized through the detailed steps shown in FIGS. 1(4) to 1(F), for example.

As shown in Figure 1 (4), Nwe II is applied to the P-type Si substrate.
Form a region. Thereafter, as shown in FIG.
l Fi, all covered with resist. Next, the silicon nitride film is etched using this resist pattern as a mask. Next, using the resist pattern and the nitride film pattern as masks, field ion implantation is performed into the region that will become the field part of the N-type transistor (Figure 1 (C)). , perform Butter/Jung of the resist in the channel area. In this case, the entire N-type Tv side is covered with resist.

Using this resist pattern as a mask, silicon nitride is etched, and using this resist pattern and the silicon nitride film pattern as masks, field ions are implanted into the region that will become the field part of the P-type transistor (see Figure 1 (trout)). After that, the resist is removed and a gate oxide film, a gate electrode, etc. are formed to complete the CMOS semiconductor device. According to the present invention, the number of light exposure steps required to complete field ion implantation can be reduced by one. Furthermore, during ion implantation, all portions where ions are not implanted are covered by a thick resist layer, so that ions are not implanted through the entire region.

[Brief explanation of the drawing]

FIGS. 1(4) to 1(F) are cross-sectional views showing the process of manufacturing an OCMOS semiconductor device according to the present invention. Figures 2 (4) to (2) are cross-sectional views showing the process of manufacturing a CMOS semiconductor device using a conventional method. In the figure, 1. P-type 8i substrate 2, Nwell region 3, silicon oxide film 4, silicon nitride. Film 5, resist 6, P-type silicon region 7. N-type silicon region 8, polysilicon gate agent Patent attorney Kensuke Chika (Ill! 1 person) Diagram (C)

Claims (1)

[Claims] In the process of manufacturing a complementary MOS semiconductor device, a step of forming a pattern in a region where one conductivity type transistor is to be formed and a step of forming a pattern in a region in which an opposite conductivity type transistor is to be formed are performed separately. A method for manufacturing a semiconductor device.