JPS6167320A - Josephson ad converter circuit - Google Patents

Abstract

PURPOSE:To convert analog input signals into digital signals having large bit numbers in a wide range of values, by using two kinds of Josephson gate circuits equipped with control line having different threshold characteristics. CONSTITUTION:Josephson gate circuits Q1-Qn equipped with control line which are formed by using Josephson junction devices which take zero-potential states and potential-existing states between output terminals 4 and 4' in accordance with control currents given to control current lines H1-Hm are provided. Both ends of each control current line Hi are connected with the pair of output terminals of each control-line-equipped Josephson gate circuit Mij. When analog input signals are supplied with equal or different values to the control current line of the gate circuit Mij, n-bit digital signals are outputted from the output terminal of the gate circuit Qi. Therefore, analog input signals can be converted into digital signals of high bit numbers in a wide range of values.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a Josephson AD conversion circuit constructed using Josephson junction elements.

2. Description of the Related Art As a Josephson AD conversion circuit constructed using a Josephson junction element, one having the configuration described below with reference to FIG. 1 has been proposed.

That is, the control current I has a bias current line 1 and control current lines 2 and 3, and is supplied to the 1ilJ Ill current line 2. and the value of the bias current I supplied to the bias current line 1, between the output terminals 4 and 4',
It takes a zero voltage state or a voltage state, and its threshold characteristic for taking the zero voltage state or voltage state has a periodicity that is different from each other with respect to the value of the control current IC supplied to the control m+ current line 2. , a plurality of n1liii two-terminal Josephson gate circuits with control lines M1, M2, . . . Mn configured using Josephson junction elements.

In this case, control lines I, Josephson gate circuits M, M
2...M is the control current r supplied to the control current line 2, as described above. Depending on the value of and the type of bias current lb supplied to bias current The threshold characteristic has a periodicity of mutually different periods for one cycle of the control current (2) supplied to the control current line 2. 2・
・・・・・・・・・N) The period of the above-mentioned threshold characteristic is set to 1.
As shown in Figure 2, the period [, is 2
It has a period of (i-1)×1.

In addition, the control line f=j (on the threshold characteristic of the Josephson gate circuit M1), the period I・(=2(i-1)×1,)
The periodicity with the control l] current line 3 is controlled from the bias current line B, as will be described later, so that the control i1] current 1 [but with the value I
By being supplied with '', as shown in Figure 2,
If l((() of control current 1c is zero, bias current I
has a phase such that b has the value ■'.

Such a Josephson gate circuit M with control line is -
As an example, it has the configuration described below with reference to FIG.

Firstly, three Josephson gate circuits with control lines F1 and F2 have a configuration in which a Josephson junction element 6 is inserted in the bias current line 5, and control current lines 7 and 8 are magnetically coupled to it. and F3.

The bias current lines 5 of these Josephson gate circuits F1 to F3 are connected in parallel, and the parallel circuit is inserted into the bias current line 1 described above.

In addition, control 21 of the Josephson gate circuit F-F3
An I current line 7 is connected in series and inserted into the control current line 2 described above.

Further, the control current lines 8 of the di-Sefson gate circuits F1 to F3 are connected in series and inserted into the above-mentioned control current line 3.

Furthermore, the above-mentioned output terminal 4 is connected from both ends of the parallel circuit of the bias current a5 of the Josephson gate circuits F1 to F3.
and 4' are derived.

The above is Josephson gate circuit M with control line.

There is an example structure.

The bias current lines 1 of the Josephson gate circuits M1 to Mn with control lines having such a configuration are connected in series and inserted into the bias current line 11, as shown in FIG.

Also, the control current of Josephson gate circuits M1 to M with control lines! ! 22 are connected in series to input current line 12.
is inserted.

Furthermore, Joseph song gate circuit 1 (1
1 control current P;A3 is inserted into the control current line B1.

Further, a load is connected between both ends 4 and 4' of the Josephson gate circuit M with a control line.

The above is the structure of the Josephson AD conversion circuit that has been proposed in the past.

According to the Josephson AD conversion circuit having such a configuration, when the bias current I is supplied to the bias current line 11, the bias current I is supplied to the bias current line 1 of the Josephson gate circuit M with a control line. , is supplied with that value.

Furthermore, if an analog input current I is supplied to the input current line 12, an analog input current I is supplied to the control current line 2 of the Josephson gate circuit M with a control line as a control current at that value. be done.

Furthermore, if the control current 1 is supplied to the #A control current line Bi, the control current 1 of the Josephson gate circuit Mi with the control 2111a is
A control II current I" is supplied to the 2Il current line 3 at that value.

Therefore, the bias current I to be supplied to the bias current line 11 is selected to be the value I' mentioned above, and b
b Also, the control current l supplied to the control current line B.

By selecting the above-mentioned value 1', the above-mentioned threshold characteristic of the Josephson gate circuit M with control line becomes the second The figure shows the same out-of-period as described above.

In other words, if the axis of the control current IC in FIG. 2 is the axis of the analog input current I, there is a cycle of Ic.

Therefore, now, let the value of 1/2 of the above-mentioned period 11 be I, and in relation to the value of the analog input current [8 as 1, the following value III g-sl's2'' S3... ....I.

2n O≦r　sl〈[.

■ ≦[, 2<2X[.

2X[≦[33<3XIq 3×1　　≦I, 4<4XI.

4X I ≧) s5 < 5x Ig (2-1) x I ≦ [<2 But the values 1 sl, r s3. I s5...
..." If it has s(2n-1), it assumes the zero voltage state, but if it has the value II...I and s2゛s4 s2n, then it takes the zero voltage state. As shown by the X mark in A, the voltage is applied.

Furthermore, the Josephson gate circuit M2 with gfJi has an analog input current I between its output terminals 4 and 4' of values I and II and 6°S 51
321 S5”' ”・””s(2n-3)
and l5 (2n-2), it assumes a zero voltage state, but the values 's3 and I34''37 and 1 °''''''
When it has ``°''''``'' s (2 rows 1) and I, it assumes a voltage-applied state as indicated by the X mark in FIG. 2B.

Furthermore, the Josephson gate circuit M3 with a control line has an analog input current I between its output terminals 4 and 4' with a value '
si~Bow 4"39~1,12..."'''' I s
(2nzu) has s(2n-4) ~ (2), it assumes a zero voltage state, but Is5 to Is8. Isl~
I ......l3 (20-3) ~ Take r 3 sl6
In the case of s2n, as shown by the X mark in FIG. 2C, a market pressure state is assumed.

In this way, the Joseph Song (-circuit M) with control line has an analog input current I between its output terminals 4 and 4'. (3x2”
-” ) ~ I' 5 (4x2 Rollo + IJ 5 (5x2
If the voltage has a value of ``-re), it assumes a zero voltage state.

In addition, the analog input current ■, between the output ends 4 and 4' of the control powder-equipped Jisan Ruffson Goo 1 to circuit M is ~ I's (21+ -th + i) 5 (2x2''
−” )' 5 (3x2 ” ” +1)
5 (4x2 ”-mouth) ~ I ■5 (5x2 ray-II, B 5 (6x2 + l
-11) ~ If it has a value of I, change the voltage state to Ij.

Therefore, now, Josephson gate circuit with control line M1~
The voltage (zero voltage) obtained between output terminals 4 and 4' when ~1o assumes a zero voltage state is indicated as "0" in the two-direction display, and the voltage obtained between output terminals 4 and 4' when it assumes a voltage state is If we take the voltage (voltage) that is 1q between 4' and NJ in binary display, the analog input current ■ is III...5S11
If S2'S3,■ has (11'i) s(2n-1)s2', then between the output terminals 4 and 4' of the Josephson gate circuit M1 with control line,
As shown in Fig. 4, rOJ, rlJ, rOJ...
...Digital output of rOJ and rlJ can be obtained.

Moreover, between the output terminals 4 and 4' of the control line attached to Joseph Song 1 and the circuit M2, there is a rob, a rob.

NJ, rlJ, rOJ, rOJ... "O
J.

Digital outputs of roj, Ml, and NJ are obtained.

Further, between the output terminals 4 and 4' of the Josephson gate circuit with control line M3, there is a rob, "QJ".

rOJ, rob, rlJ, rlJ, rlJ.

rIJ, rOJ, rob, rol, r
l ・・・・・・・・・ [OJ, ro'J,
rOJ, rOJ, rlJ.

The digital 81 power of MJ, rlJ, rlJ is (7).

In this way, control (Joseph song gate circuit M with 2II line)
An analog input current ■8 is applied between output terminals 4 and 4' of 1.
1") ~ ■ '5 (4x 2" ++) 5 (5x 2"
- days) ~ I, a digital output of "0" is outputted.

Moreover, between the output terminals 4 and 4' of the Josephson gate circuit M with control line, the analog input current I3 is
i-II)~I! 5(3x2 + + -++ +1) ~l5(4x
2 , , -, , )' 5 (5X 2nd day -th + 1)
If it has a value of 5 (6×2 day-th) to I, a digital output of “1” is outputted 1q.

Therefore, from n loads, L2...l-o,
If the analog input current I has a value of 'sl, then
(rob, rOJ . . . [OJ) n-pi 1- digital output is obtained.

Furthermore, when the analog input current I has a value of Is2, (rlJ, r○", "○"......"
n-bit digital output of (!7).

Furthermore, when the analog input current I has one shift of 1 and 3, (rOJ, rlJ, rOJrOJ...
. . . "O") n-bit digital output is jq.

Thus, from the load 1 to L, an n-bit digital output representing the value of the analog input current is can be obtained.

Also, a device having the configuration described below with reference to FIG. 5 has been proposed.

That is, bias current lines 1 and 1' and control current line 2
．． 3 and 9, and the control current line 9 has a control current 1r.
H supplied to the control current line 2,
II 12II The value of the current 1° and the bias current ■ supplied to the bias currents tA1 and 1'. Depending on the value of
Between the output terminals 4 and 4', a zero voltage state or a voltage state is taken, and the control current I supplied to the control current line 2 is n i!i'l iII constructed using Josephson junction elements, each having the same periodicity for one shift.
It has linear Josephson gate circuits M1 to M.

In this case, Joseph Song 1 to circuit M with control line are as follows:
Above: As shown in E, the Hill ifl + current line 9 is controlled (
(b) When the current I is being supplied, the value of the control 2+1 current IC supplied to the control current line 2 and the bias current line 1
and the value of the bias current Ib supplied to Cm and 1', a zero voltage state or a voltage state is taken between the output terminals 4 and 4', and a threshold characteristic that takes the zero voltage state Cm or a voltage state, H for the control current IC supplied to the control current line 2 has the same periodicity, but now the period of the threshold characteristic described above of the Josephson gate circuit M with control line is expressed as r
Then, the period Ii of the threshold characteristic of the Josephson gate circuit M with the control 1IFA has the period 11 described above in the case of FIG. 1, as shown in FIG.

Therefore, the periods of the periodicity of the threshold characteristics of the Josephson gate circuits with control lines M1 to M1 have the same period 11.

Also, Joseph Song Gate Circuit M with control l1FA.

As shown in FIG.
. When the value of is zero, the bias current 1b is equal to (i) the value Ib' mentioned above in the case of FIG.
1.

Such a control 11A ('J Josephson gate circuit M.) follows, by way of example, the configuration described below with reference to FIG.

In addition, a Josephson gate circuit 21 with a control line has a bias current line 31 and control current lines 32 and 33.
has.

This control line (・1 line is connected to the circuit 21, which is connected to the bias current line 1, is connected to the bias current line 1, and the bias current line 1 is connected to the bias current line 1). The control lines f"Joseph Song 1-
The configuration of circuit M1 and +ti is modified.

Therefore, the control line (J Joseph Song-1 circuit 21 is
Josephson gate circuit with control line M1 described above in FIG.
In the explanation of the threshold characteristics of d3, bias current line 1. System (
2Il current lines 2 and 3 respectively to bias current lines 31.
Control current! Except for reading 232 and 33,
Josephson gate circuit with control line M1 described above in FIG.
It has a threshold characteristic explained similarly to . It also includes other Josephson gate circuits 22, 23 and 24 with control lines each having a bias current line 31 and a control current line 32.

These rules! Josephson gate circuit with Il line 22゜23
and 24, the control 11 current line 3 is omitted in the Josephson gate circuit with control line M1 described above in FIG. 7 is omitted, and the bias current line 1 and control current line 2 are
It has the same configuration as the Josephson gate circuit with control line M1 shown in FIG.

However, the control line I"Josephson gate circuit 22.23
and 24, while the control current is being supplied to the control 211 current line 32 at the scheduled rate, the bias current supplied to the bias current line 31 is at the scheduled level l+TIJ.
It has an IJliO characteristic that it takes a zero voltage state if it is less than a predetermined value, and takes a voltage state if it is more than a predetermined value.

Thus, the bias current line 31 of Joseph Song Gate circuit 21 with control line and the control current line 32 of Joseph Song Gate circuit 24 with control line 21I are connected in series, and the resistors 25 and 26 are connected in series. The bias current line 1 described above is inserted into the bias current line 1 in turn.

Furthermore, the high current 1'1131 of the Josephson gate circuit 22 with the control llI line and 1. The control line fζ1 and the control current line 32 of the circuit 23 are connected in series, and are inserted into the aforementioned bias current line 1' through the resistors 27 and 28 in that order. Note that one ends of the bias currents \A1 and 1' are connected to a common end (ground).

Further, one end of the bias current line 31 of the circuit 23 to the control line (=J Joseph Song 1) is connected to the grounding medium of the above-mentioned resistor 25 and 2G through two resistors, and the other end is connected to the bias current line 31 of the circuit 23. Connected to the common end (ground) of lines 1 and 1'.

Furthermore, one end of the bias current line 31 of the Josephson gate circuit with control line 24 is connected to the connection midpoint of the above-mentioned resistors 27 and 28 through the resistor 30, and the curved end is connected to the common end of the bias current lines 1 and 1. It is connected to the.

Further, both ends of the resistor 34 are connected to both ends of the bias current line 31 of the Josephson gate circuit with control line 23, and
Both ends of the resistor 35 are connected to a Josephson gate circuit 24 with a control line.
The bias current line 31 is connected to both ends of the bias current line 31 .

Roughly speaking, the control current line 32 of the Josephson gate circuit with control line 21 is inserted into the above-mentioned control current line 2, and
A control current line 33 of the Josephson gate circuit 21 with 30 control lines is inserted into the control current line 3 described above.

In addition, the control ITi flow line 32 of the control line 1 inch Josephson gate circuit 22 is inserted into the control current line 9 described above.

Further, from both ends of the resistor 34, the above-mentioned output terminals 4 and 4'
is being questioned.

The above is an example of the configuration of Joseph Song 1 to circuit 11 with control lines.

Joseph Song 1- with control line having this kind of configuration
Each of the circuits M, , M2...M3 is
Bias currents 1 and 1' of A are inserted into bias current lines 11 and 11', respectively, as shown in FIG.

On the other hand, the input current FJ12 is connected to the resistors R, R1゜R,...
. . . The control current of the Josephson gate circuit M with control line is assumed to be connected in series with Ro, and in this case, one end of the input current line 12 is grounded! One end of Q2 is in contact with the resistors R- and R1 via the resistor R' (i 1
) and the other end is grounded.

Furthermore, the control current lines 3 and 9 of the Josephson gate circuit with control line 1'V11 are connected to the control current line Bi.
and G, are inserted.

Furthermore, a load is connected between the output terminals 4 and 4' of the Josephson gate circuit M with a control line.

The above is another example of the conventional Josephson AD conversion circuit.

According to the Josephson AD conversion circuit having such a +M configuration, if bias current b is supplied to the bias current lines 11 and 11' for the Josephson gate circuit M with control lines, the Josephson gate circuit with control lines M circuit M,
A bias current 1b is applied to the bias current lines 1 and 1' of
supplied at that value.

Furthermore, if the control current 1. is supplied to the control (21I current line B1), the control (fl
A control current I[ is supplied to the I current line 3 at that value.

In addition, if the analog input current ■ is supplied to the input current line 12, the Josephson gate circuit with control line M・2M2・
The analog input current I3 is applied to the control current line 2 of M, (Is-1), (
The values of l5-2>--.--(Is-n) are respectively supplied as control currents IC.

In this case, the ratio of the analog cog input current ■, is [(18-
1)+((s-2)+・・・・−・−(1゜−口)1), but the value of resistance R, R,, R2......The value of R, the resistance R ',R' ・・・・・・Rln
By appropriately choosing the value of 1 2', the values (1-1), ([-2), ([,-
3) . . . (Is 8-n) has the following relationship.

(1-2)=(r,-1)xi/2 (1,-3)-(13-1)X1/4(1-4)-(
1,-1)X1/8 ([-n)=(1-1)x1/2(0”S Therefore, control of Josephson gate circuit Mi with control line!2
11 current line 2, a log input current 18 is N −1
)Xl/2"' fin.

Therefore, the value of 1/2 of the period 11 mentioned above is set to 1 g as in the case of FIG. 1, and the analog input current is I is the value ([.

-1), the value of its analog input current I, (
1, -1) with I, the following 41 (11) 1° ([-1)...
......(1-1) Let n be.

S2s
20≦(1-1>1<1゜1≦l[-7n2〈2×I.

S 2×1　≦(1-1>3<3Xf.

3XI ≦(1-1>4<4xl.

S (2-1) XI ≦ (1-1), .

S < 2
11) , (1-1) 5... Old...
・If it has (■3-1) (2n-1), it will be in a zero voltage state, but 1 direct (1-1), (r
-1> , (I -'S 2
S 4 sl)・
・・・・・・・・・(1-1) 6 with , , on the right
s 2, the voltage is applied as shown by the X mark in FIG. 6A.

In addition, the analog input current I is supplied with the value (1, -2) to the control current line 2 of the Josephson gate circuit with control line M2, and the analog input current I is #J (1, -2). )
In relation to Ig, the following value (f −2>,
(1-2>, (1s 1
s23-2) ・・・・・・・・・
・(1-2) , .

3 S 20≦(1,
-2) 1<1/2XI.

1,/2 X I ≦(1-2>2<IgQ
S1≦(r-2)3<3/2xr.

S 3/2X I ≦ (12) 4 < 2 XI qS (2,-1>/2x [g≦ ([-2). ＜2　x■.

In that case, the circuit M2 with the control line 2Il will have an analog input current I between its output terminals 4 and 4' with the values (1-2)1 and S (1-2), (1 −2>5 and (■, −s
2 s 2) ......<1 -2) n and (I36 s (2-3)
-2) n takes the zero voltage state, but the value (1-2>3 and (IS-2)4, (1-2)
and (1-2>8......s
7 S(12) n- and (12>
When zn has s (21) s, the voltage state is assumed as shown in FIG. 6B.

Furthermore, control 1 of Josephson gate circuit M3 with control line
] Analog human power to current line 2 [heart flow 18] is the value (1, -3)
The value of its analog input current I, supplied by 4 −3
), in relation to I, S S next value (r −3), N −3)2...
...S 1 5 (+ -3) n.

0≦(I-3)1<1/4XIg 1/4XI ≦(1-3)2<1/2xl.

S 1/2XI ≦(1-3)3 ＜3/4x1gS 3/4x [+ ≦ (Is-3)4 ＜IQ■
≦(1-3>5<5/4x1gS (2-1)/4≦<1-3)2゜<2/4X[9 However, the Josephson gate circuit M3 with control line has its output terminal 4 and 4′ C゛, analog input current I
But the value N -3) 1~(IS, 5 S-3) , (1-3) 9~(1,-3>1□S -・==(13) n-~(13)(2s
(27) s. -4), it assumes a zero voltage state, but (1
-3) ~ (1-3) , (IS-3)S
5 S 813”””
(13) 1e""...' (1, 3) (2n-3) ~
(1-3). In this case, the voltage is applied as shown in FIG.

In this way, an analog input current I is applied to the control current line 2 of the Josephson gate circuit M with a control line.

is supplied with the value (I5-1), the analog input current I'
fii'1 (Is-i) of s, in relation to Ig, the following I (l i), (I 1)2...
...s 1 s (1+) n.

(-1)・I9 0≦(1-1)1<1/2 2X1/2"' xl ≦2X([-1)1S n (i-1) (2-1) X
1/2 x 1g≦(+ =>2゜n (i-1) < 2 Between ', the input current I, is ■ -1) ~ (I i)2 +: -s
1 s (I 1) (2×2+・-day+1) ~ (1') (
3X2"-mouth) (1!) (4x2't-+++1
)'(l 1) (5x2+1-++) of l(i 庖(1 and C), take the kanden loaf-shaped r nail.

In addition, the line 11υ11 line A1 Joseph Song 1-Circuit N1° is connected between its output terminals 1 and 4' (, Analog 1' input terminal ■ is (1!) (2+ t - II N) 〜(1ri(2×2+・−1■ (1i)(3×2+: −++ +1)〜(I −
・)(4X2・・−・・)(1: )(5X2+
+−+(+1)～(I l )(6x21r −+
+), change the right voltage state.

Therefore, now, Johifusonge 1 with control line - circuit M1
The voltage obtained between the output terminals 4 and 4' when ~M assumes the zero voltage state (rOJ of the answering signal, and 1q between the output terminals 4 and 4' when it assumes the right voltage state) If the voltage applied (voltage) is "1" on a binary display, the analog input current I is the control line I'Josephson gate circuit M
The control current PII2 is supplied to the control current line 2 of the Josephson gate circuit M1 with a control picture (i-1) (1 to 1) with the value of (IS-)). Since the analog input current ■ is supplied, Lll
! In terms of the value supplied to the control current line 2 of the Josephson gate circuit M1 with 2'Il line, it is ([-1), -1)2...... (13S 1 3 -1) If it has a value of 2n, a, II fil wired jaw is connected between the output terminals 4 and 4' of Fusonge-1 circuit M, as shown in FIG. A digital output similar to that described above is obtained.

Therefore, from the loads L1 to L, an n-bit digital output representing the value of the analog input current 2 can be obtained.

The problems that R. The above-mentioned periodic threshold characteristics of the circuit M are the first, second,...
The maximum value of b (bias current taken in the cycle 1) decreases as the number of cycles 1vI increases.

For this reason, the aill tflll line (=j Joseph Song 1 - the control 1llI of the circuit M
When the control current IC takes a value higher than a certain value, the control line (q
Even though the circuit M should take the voltage state, it does not take the voltage state.

This will cause a malfunction.

Therefore, the Jollefson gate circuit with control line is limited to the maximum of the control current l. supplied to the control current line 2 of V1, and therefore the maximum i1/+ of the analog input current I, and the analog The input current is limited to the number of input currents (the range of values up to the maximum value of 3), that is, n Ml.

Therefore, according to FIGS. It had the disadvantage that it could not be converted into a large digital output.

By means of solving the problem, the present invention converts the above-mentioned analog input current into a digital signal with a larger number of bits over a wider range of values than in the case of conventional Josephson AD conversion circuits. The purpose of the present invention is to promote a new Josephson AD conversion circuit that can perform the following steps.

The Josephson AD conversion circuit according to the present invention has the following configuration.

In other words, it has a bias current line and a control (II current line), and a pair is determined depending on the value of the control current supplied to the control 21I current line and the value of the bias current supplied to the bias current line. takes a zero voltage state or a voltage state between the output terminals of the control current line, and the threshold characteristic for taking the zero voltage state or voltage state has a period that is different or the same for the value of the control current supplied to the control current line. Using a Josephson junction element with a periodicity of lvl
21~~12m knee......has Mn1~Mnm.

In addition, the bias current line and the control current of m rotations: jH1 ~
I-1 m, and the control current line H1 to 11I is an even number ν among the control 21I current lines. Is it paid?
fi'l t2'11 The control 211 current is 2 in the odd numbered control current lines in the current line t11 to t1m.
Using Josephson junction elements (14 formed n 1i (
The I line terminal has fuson games 1 to circuits 01 to Q.

Therefore, ii of Josephson gate circuit Q1 with control line
l control control current line (j = 1, 2-...
Both ends of −m > are Josephson gate circuits with control lines ~
1.(i=1.2......n) are connected to the output terminals of the pair.

According to the Josephson AD conversion circuit according to the present invention, the Josephson gate circuits with control lines M11 to M1m
;M21~M2m '''``''' Mn1~M
. By supplying analog input currents with the same or different values to the control current lines □, the analog input current is supplied from the output terminals of the pair of Josephson gate circuits with control lines 01 to Qo. An n-bit digital output is output.

In this case, the periodic threshold characteristic of the Josephson gate circuit M between control lines is similar to that of the conventional Josephson gate circuit M with control lines described above in FIGS. , second...
It exhibits a threshold characteristic in which the maximum bias current (direction) taken in the cycle number decreases as the number of cycles increases.

For this reason, when the control current supplied to the control current line of the Josephson gate circuit with control picture takes a value greater than the J value, the conventional Josephson gate circuit with control line As in the case of the circuit Mi to the song 1, the control line 3I? Fuson gate circuit M1.
A malfunction occurs in which the voltage does not take the nail voltage state even though it should take the right voltage state.

Therefore, f of the Josephson gate circuit M1j with control line
Maximum 1i of control 12Il current supplied to f1lJ control current line
D. Therefore, the maximum analog input current is limited as in the case of Figures 1 and 5, and the range up to the maximum value of the analog input current is limited by the number, size, etc. Limited to 11ti of n.

However, in the case of the Josephson AD conversion circuit according to the present invention, the control line equipped Josephson gate circuit MIJ
Within the same control current range, the number of cycles 1σ1 in the direct characteristic f1 is calculated as follows from Lt described above in FIGS. 1 and 5:
3I? Fuson AD change 1st circuit; J5 () control line I.
'' can be reduced to 1/m of the Josephson gate circuit M.

Therefore, the maximum fi+T of the ail O1l current supplied to the control current line of the Josephson gate circuit MIJ with control line
Therefore, the maximum analog input current can be made m times that of the conventional Joseph-Sonno Δ1 conversion circuit described above in FIGS. 1 and 5.

As a result of the effects of the present invention, the Josephson AD converter circuit according to the present invention can control the analog input current over a wide range of m times as compared to the conventional Josephson AD converter circuit described above in FIGS. 1 and 5. It has the feature that it can convert values into digital outputs with a large number of bits.

Embodiment 1 FIG. 8 shows a first embodiment of the Josephson AD conversion circuit according to the present invention, which includes nm (n≧2, m≧2) Josephson gate circuits with control lines M111M12.・・・・・・
・・・・・・MllIl；M212M22・・・・・・
・・M21Il；・・・・・・・・・”n12Mn2・
......It has Mol1l.

In this case, Josephson gate circuit M (1 to M
1□ has a configuration similar to that of the Josephson gate circuit Mi with control line described above in FIGS. 1 and 3.

Therefore, Josephson gate circuit with control line M11~lV
lim, the same reference numerals 4 are used for parts corresponding to those in Figure 1.
fζ] and omit the explanation of Rev. 11.

In addition, the control line I"Josephson gate circuit M11-M1
-If the period of the period 1/jI is [, then the period 1
1 has a period of 2.times.11, as shown in FIG. 9, as in the case of the control line I4Joleffson gate circuit to 1 (i-11) described above in FIG.

However, in this case, Josephson gate circuit with control line M
Period 11t, t of threshold 1 direct characteristic of 11 to M1□, period 19 of threshold characteristic of Josephson gate circuit M1 with control line in Jj in the conventional Josephson AD conversion circuit described above in FIG.
] has a value of mjg of 11.

Also, bias current line 1 and m control 11 currents! ! 1
1+-1, 12.・・・・・・・・・H□ and control f
Il current line 3 and m control ft1 current lines H1~
The control@current is displayed in two values on the even numbered control current lines in H□.
1" (or "O"), or the control l is supplied to an odd number of control current lines among the m control current lines G11 to FIII1.
'rri style 1fi binary display
J) A plurality of n Josephson gates with control lines constructed using Josephson junction elements, which take a zero voltage state or a voltage state between output terminals 4 and 4' depending on whether the voltage is supplied. Circuit Q1. Q2・・・・・・・・・Qo
and has.

This Josephson gate circuit Q with control line.

(i=1.2......n) may have various configurations that are known per se, but as shown in FIG. 10, In the configuration of the Josephson gate circuit M with control line, the control current line 2 is m
The control current lines H1 to HI11 are changed to the main control current lines H1 to HI11, and accordingly, the control current lines of the Josephson gate circuits F1 to F3 are changed to 7 (instead of 1 tree, there are m lines, 1, and the Josephson gate circuit jth of F1 to F3 (j=1.2...
.....m) is connected in series and inserted into the control current line ('').
The diagram on the right shows a configuration similar to the Josephson gate circuit with control line M1 described above.

Therefore, Josephson gate circuits with control lines M11 to M
1m1M21~” 2m,”・”・”・Mnl~M,-
A bias current line 1 is connected in series and inserted into a bias current line 11.

In addition, Josephson gate circuits with control lines M11 to M11
Il1M21~M2m,......~'nl~
M, 1. Il a, ++ l2il current lines 2 are connected in series and inserted into the input current line 12.

Furthermore, the control current line 3 of the Josephson gate circuit with control line ~11 is interposed in the control current line B.

Further, the bias current lines 1 of the Josephson gate circuits Q1 to Qo with control lines are connected in series and inserted into the bar current line 41.

Further, both ends of the control current line Hj of the Josephson gate circuit with control line Qi are connected to the outputs J and inner ends 4 and 4' of the Josephson gate circuit with control line M through the resistor R1. .

Furthermore, a load L 1a is connected between the output terminals 4 and 4' of the Josephson gate circuit Qi with a control line! I'm here.

The following is the configuration of the first embodiment of the circuit according to the present invention.

According to the Josephson AD conversion circuit having such a configuration, when the bias current Ib is supplied to the bias current line 11, the bias current Ib is supplied to the bias current line 1 of the Josephson gate circuit with control line M. Ib is supplied at that value.

Furthermore, when the analog input current I8 is supplied to the input current line 12, the analog input current J I is supplied to the control current line 2 of the Josephson gate circuit M with a control line, and becomes the control current 1 at that value. Supplied closed.

Furthermore, a control current 1.0 is applied to the control current line Bij. , the control I lightning current f is supplied at that value to the control current line 3 of the Josephson gate circuit MiJ with control (21I line).

For this reason, the bias current I supplied to the bias current line 11 is selected to be the value 1b' described above in FIG. 1, and the control current If supplied to the control i current line Bij is selected to an appropriate value. Josephson gate circuit M, with control line.

The above-mentioned threshold characteristics of 1.1 impose the same periodicity as described above in FIG. 9 for the analog input current I supplied to the input terminal line 12.

In other words, the axis of the flil control current IC in FIG. 9 is set to the analog input current 1. The periodicity on the axis is right.

However, in this case, all current lines B11. B12...
......B11R is supplied with all the control current l', therefore, the control line example is 111? Fuson gate circuit M
145M12...M13 control current line 3
By making the values of the control current 1f supplied to J different from each other, the Josephson gate circuit with control line M119M
12...The phase of the directivity characteristic of M1□ is sequentially different from the phase of the threshold characteristic of the Josephson gate circuit with control line M11.

For example, when the threshold characteristic of the Josephson gate circuit with control line M11 is such that when the control [I current 1c is zero and the bias current lb has a phase of zero, 1n holds between the control line and Josephson gate circuit M12. The characteristic phase has a phase difference of 1/4×11 with respect to the phase of the threshold characteristic of the Josephson gate circuit with control picture M.

In this way, the control current FAMiL ``i2...
... M Therefore, by making the values of the control currents I supplied to the control current lines 3 of the Josephson gate circuits m1 Mli ''i2' ...Mim different from each other. , Josephson gate circuit Mi with control line
1. The phase of the threshold characteristic of "i2...Mill" is sequentially different from the phase of the threshold characteristic of the Josephson gate circuit M11 with control Il line.

For example, if the threshold characteristic of the Josephson gate circuit M11 is that the control current IC is zero, then the bias current I
bh<0, the phase of the threshold characteristic of the Josephson gate circuit M12 with control line is (1/4 x 11) x i with respect to the phase of the threshold characteristic of the Josephson gate circuit M11 with control line. Has a phase difference.

Therefore, now, let the value of 1/2 of the above-mentioned period 11 be 1, and the value of the analog input terminal IRI, in relation to IQ, be the following value [sl, I B2 . l B3...
・・・・・・・・・■ Do1).

s2' mockery O≦Is,,<1/2XI.

1/2XI ≦1 <1 s2g I≦I, 3〈3/2X1g 3/2X I ≦ 1. <2X Summer.

2XI ≧I85<5/2XI.

(2-1)/2xl ≦l52n <2 /2X[g In that case, J9 Sefson gate circuit with control line M11
has an analog input current I between its outputs 4 and 4'
But ff1I and II and s
sl B2゛ B5bi'B6'''”
・"" When it has s(2n-3) and 's(2n-2), it takes a zero voltage state, but the values 's3 and 's4
．． 's7 and 1,8...1. (2゜-1
) and 1, mark 32 with an x in Figure 9A.
゜Takes the right voltage state as shown.

In addition, circuit M12 to Joseph Song 1 with control I line is,
Between its outputs 4 and 4', the analog input current l is
Value ■ and II and's7...s
s2 s3゛ s6”' ”” s(
2n-2) and l5 (2n-1), the zero voltage state is returned, but the values 'sl, Is4 and Is5°''
``'''''s(2'-4) and 's(2'-3)
When it has I, it assumes a voltage-applied state as shown by the X mark S2° in FIG. 9B.

Further, the Josephson gate circuit with control line M21 has analog input currents `s1 to `s4' between its output terminals 4 and 4'. Is9~I, 12...”' ””
s(2n-7) has s(2'-4) ~
I, the zero voltage state is assumed, but the value ■s5 to IS8. ■51
2315~rwo~ ” ”’ ”’ ”” S (2ro -
3) If S20 is present, X in Figure 9C
As shown by the mark, the voltage is applied.

In addition, the Josephson gate circuit M22 with control iIl line is
Between its output terminals 4 and 4', the analog input current ■ is
Value ■ and I [~I s s3 s6・sll S13
. . . , the zero voltage state is assumed, but the value 1sl and S2. IS1~[S11...
When rS(2n-1) and

Furthermore, a Josephson gate circuit with control line (ν131
is its output; between 4 and 4', the analog input current I
But the values 's1~'s8. rs17~' s24・
If ・・・・・・・・・ is on the right, the right voltage state is returned, but r-r, r ~ 1 ・・・・・・・・・
If the current is s9, S16, S25, S32, the right voltage is <g, as shown by the X mark in FIG. 9E.

In addition, the ll11j valley Il line f=J dioseno song one circuit ~132 has its output terminals 4 and 4M;
1 -1s s5 S12 S21
In the case of JA with S28......, the zero voltage state is assumed, but
.

In this way, the Josephson gate circuit Mij with ml+121I line assumes the zero voltage state 5 or the right voltage state at its output terminals 4 and 4'12S+ in response to the current of the analog input current I.

Therefore, now, Josephson gate circuit with control line "11
~M1o0M21~M2r "'"・"'"nl-",
Their outputs 4 and 4' when m assumes a zero voltage state
The voltage (zero/voltage) obtained between
0", and the voltage obtained between output terminals 4 and 4' when the voltage is applied (voltage) is set to "1" on the 21 direct display.
Then, the analog input current ■ is I I
I---I, (2n -1s slo s
2゛s3, if it has the value of I, the control line is attached) s
Between the output terminals 4 and 4'J of the 2° Josephson gate circuit M, n=3. In the case of m=2, as shown in Fig. 11,
Digital output can be obtained.

Also, n=3. When m=3, a digital output of 1q is provided between the output terminals 4 and 4' J of the Josephson gate circuit M with control line, as shown in FIG.

Therefore, Josephson gate circuits with control lines Q1 to Qo
Therefore, n=3. When m=2, the digital output is 19 as shown in FIG.

Also, n=3. When m=3, the digital output is 14 as shown in FIG.

Therefore, with a load of 1 to L, n digital outputs representing the value of the analog input current I can be obtained.

In this case, the digital output is 1, and the Josephson gate circuit with control line M11 to 111. If the number of periods J3 in the Il interval characteristic Vl is within the same control 7I'l current range value, the control line (=i Josephsonge 1 - 1/l in case of circuit M)
The monkey is q.

Therefore, as shown in FIG.
In the case of a conversion circuit, compared to the conventional Josephson AD conversion circuit described above in FIGS. 1 and 15, it is possible to convert into a digital output with a large bit lag over a wide range of m18 per shift. It has the characteristic that it can be done.

Embodiment 2 FIG. 13 shows a second embodiment of the Josephson AD conversion circuit by Bimei Ki.

In FIG. 13, parts corresponding to those in FIG. 8 are designated by the same reference numerals, and detailed description thereof will be omitted.

A second embodiment of the Josephson AD conversion circuit according to the present invention shown in FIG. 13 has a configuration similar to that of the Josephson AD conversion circuit according to the present invention described above in FIG. 8, except for the following points. .

Zunawara, circuit M to Joseph Song 1 with control line, -
Instead of having the period I of the threshold characteristic of M having 2(i-1111m1xll), the Josephson gate circuit with control line M11~M1m;
...The period of the threshold characteristic of M2n to Mn□ has rl.

In addition, the control current line 2 of the Josephson gate circuit with control line
, an analog input current I supplied to the input current line 12,
Instead of supplying the same value as that, Josephson gate circuit with control line M11 to M1111: M21 to M2m'
・・・・・・”' M2n” Mnm’s 111112
In the conventional Josephson AD converter circuit described above in FIG.
input terminal I, becomes H (5+, + (direct (IS-1>,
(1-2)・・・・・・・・・(1-n) supplies S
As in the case of S, 5'1: becomes 1100 ([S-1>, (IS-2)
. . . ([, -n).

Therefore, as described above in FIG. 5, the input current line 12
, resistors R, R, R2, ......Ro are inserted in series, and in this case, assuming that one end of the input current line 12 is grounded, the control line The control current lines 2 of the attached Josephson gate circuits M・~M, □ are connected in series, and one end of the control current line 2 is connected to the connection midpoint of the resistors R(i-1) and R, via the resistor R,l. and the other end is grounded.

The above is the second part of the Josephson AD conversion circuit according to this defense.
This is the configuration of the embodiment.

Josephson AD according to the present invention having such a configuration
According to the conversion circuit, it has the same configuration as that shown in FIG.

Josephson gate circuit with control line M11 to M11n
has a threshold characteristic corresponding to the threshold characteristic of the conventional Josephson AD converter circuit M with control line described above in FIG. When the analog input current I is supplied to the control I current line 2 of the circuit M11 to Mim and the control current line 2 of the circuit M to the control line 1 of the conventional Josephson AD conversion circuit, the analog input current I is the same value. Supplied.

Therefore, also in the case of the present invention shown in FIG. 13, although detailed explanation is omitted, a digital output representing the value of the analog input current I3 can be obtained with the features described above in FIG. .

Embodiment 3 FIG. 14 shows a third embodiment of the Josephson AD conversion circuit according to the present invention, in which n-m (n≧2.m≧2) Josephson gate circuits with control lines ~1□1 ~fvl 1m
;M21~M2111...Mo1~M
It has nm.

This system! 211'fA (=l) Josephson gate circuit fvlii~Mil, l is connected to the control line (
It has the same configuration as the NJ Jico Cefson Game 1-Circuit M, and accordingly, corresponding parts are given the same reference numerals and detailed explanation will be omitted.

In addition, similar to that described above in FIG.
It has Joseph Song 1-circuits Q1-Q with control lines.

Thus, the bias current lines 1 and 1' of the Josephson gate circuit with control line ~1. are inserted into the bias J currents 1A11 and 11', respectively.

On the other hand, for the input current 1i112, the resistors R, R, R,
. . . Rn are connected in series and inserted, and one end of the input current line 12 is grounded 1a. The control current line 2 of the circuit ~1~Mim is connected to the direct line, and the resistor R(i-
It is connected to the middle point of the contacts 1) and R, and the other end is grounded.

Further, the control current lines 3 and 9 of the Josephson gate circuit with control line M1j are connected to the control current lines Bij and G, respectively.
i, is inserted.

Also, Joseph song gate circuit Q with control 2a line.

Both ends of the control 2Il current line Hj are connected to the output terminals 4 and 4' of the Josephson gate circuit M1j with control line.

Furthermore, a load is connected between the output terminals 4 and 4' of the Josephson gate circuit Q with a control line.

The above is the third part of the Josephson AD conversion circuit according to the present invention.
This is the configuration of the embodiment.

According to the Josephson AD conversion circuit of the present invention having such a configuration, the Josephson gate circuit with control line Mi1
~Mim' and Q correspond to the Josephson gate circuits with control lines Mi1 to M, □; and Q of the Josephson AD conversion circuit according to the present invention described above in FIG. 13, respectively,
And Josephson gate circuit with control line Mi1~M, □
An analog input current Is is applied to the bias current line 2 of the first
Since the supply 6 is completed as in the case of FIG. 4, detailed explanation will be omitted, but the same effects as in the case of FIG. 14 can be obtained.

In the above description, the Josephson gate circuits M11 to M1m with control lines have a period of 11, and the Josephson gate circuits M11 to M1m with control lines are
JI 1 of 2(i-+) × ■ 1 period or 11 period, and accordingly, 7i! Joseph Songe with IH wire - 1 - circuit Mi1 ~ M1 - suppressor 11 current line 2,
The analog input current (I) is supplied to the control current !22 of the Josephson gate circuit M1 with a control line.

We have described the case of supplying with a value of 172 (knee 1), but the Josephson gate circuit with control line M
M ......M, the period 1 of its periodicity
1° 121m, top; ifl value is 1 lap! I] Accordingly, the control line equipped control circuit 1'
By supplying the analog input current I3 to the control current line 2 of V111 to MiI11 at a value different from the above-mentioned value, the same effect as described above (corresponding to the combination configuration of FIGS. 8 and 13) can be obtained. You can also do it to get .

In addition, various modifications and changes may be made without departing from the spirit of the invention.

[Brief explanation of drawings]

FIG. 1 is a dimensional system connection diagram showing an example of a conventional Josephson AD conversion circuit. FIG. 2 is a diagram showing the threshold characteristics of the Josephson gate circuit with control line used in this. FIG. 3 shows the control 21II! used in the conventional Josephson AD conversion circuit shown in FIG. FIG. 2 is a connection diagram of a Josephson gate circuit. FIG. 4 is a diagram showing the relationship between the analog input current and the digital output, which is used to explain the operation of the conventional Josephson AD converter circuit not shown in FIG. FIG. 5 is a systematic connection diagram showing another example of the conventional Josephson AD conversion circuit. FIG. 6 is a diagram showing the threshold characteristics of the Josephson gate circuit with an idle control FA used therein. FIG. 7 is a systematic connection diagram C of a Josephson gate circuit with a control line used in the conventional Josephson AD conversion circuit shown in FIG. FIG. 8 is a systematic connection diagram showing a first embodiment of a di=1 Kefson AD conversion circuit according to the present invention. Figure 9 t'1, - Control used for this tall FJ
(This is a diagram showing the threshold 1-direction characteristic of the 4G1j+Fsonge1 circuit. FIG. 10 is a connection diagram showing an example of the Josephson gate circuit with control line used in FIG. 8. 12 and 12 are diagrams showing the relationship between the analog input current and the digital output to explain the 05 production of the di=U-Pifson to D conversion circuit according to the present invention shown in FIG. 8. 14 is a systematic connection diagram showing a second embodiment of the Josephson AD conversion circuit according to the present invention. FIG. Yes. 1. Bias current line 2.
3......, till lit current line 4.4
' ・・・・・・・・・・・・Output end M, (i=1.
2・・・・・・・・・n) ■ ・・・・・・・・・・・・・・・Joseph song gate circuit I with 11 control wires ・・・・・・・・・・・・・・・...Cycle period B of the threshold characteristic of the control line bone Josephson gate circuit M, ......Bias current line 5
・・・・・・・・・・・・Bias current line 6...
・・・・・・・・・・・・Josephson junction element 7.
8...Bias current lines F1 to F3...Josephson gate circuit with control line 11.11'...Bias current Line Hj (
j=1.2...m)M (i=1.
2.-----n: j=1.2-J...m)...Josephson gate circuit with control line Q,...・・・・・・・・・・・・・・・Josephson gate circuit with 1 control line

Claims (1)

[Claims] A bias current line and a control current line, and depending on the value of the control current supplied to the control current line and the value of the bias current supplied to the bias current line, A zero voltage state or a voltage state is assumed between the output terminals of the pair, and the threshold characteristics for taking the zero voltage state or the voltage state are different from each other or the same period with respect to the value of the control current supplied to the control current line. Josephson gate circuits with control lines M_1_1 to M_1_m; M_
2_1 to M_2_m;...M_n_1 to M, a bias current line, and m control current lines H_1, H_2,
......H_m, and the control current lines H_1 to H_m
The control current is "1" in binary display on the even numbered control current lines inside.
(or "0") or the control current line H1
Depending on whether the control current is supplied as "1" (or "0") in the binary display to the odd number of control current lines in ~Hm, a zero voltage state or a voltage state exists between the pair of output terminals. It has n Josephson gate circuits with control lines Q_1, Q_2...Q_n configured using Josephson junction elements with Both ends of j=1, 2...m) are connected to the Josephson gate circuit with control line M_i_j (i=1, 2...
...n), and is connected to the output terminals of the pair of Josephson gate circuits with control lines M_1_1 to M_
1_m;M_2_1~M_2_m;......M_n_1~
By supplying analog input currents with the same or different values to the control current lines of M_n_m, the Josephson gate circuit with control lines Q_1;Q_2;...Q
A Josephson AD conversion circuit, characterized in that n-bit digital output representing the value of the analog input current is outputted from the pair of output terminals of _n.